Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

interval timer

Altera_Forum
Honored Contributor II
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Hi I'm new in using the altera environment and my question would be how to build a timer of 1 second with interval timer. 

The interval timer that would use it to activate an interrupt every second and so the LEDs . 

My problem is I do not understand how it works at the tiemout period and as I relate to my clock frequency is 50 MHz and to generate the second
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Altera_Forum
Honored Contributor II
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Hi, I'm also new. welcome to us :)

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Altera_Forum
Honored Contributor II
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T = 20ns (50MHz) 

 

So one second would be 1 000 000 000ns / 20ns = 50 000 000 clock cycles. You could use a free running modulo counter that starts at 0 and counts up to 49 999 999 before rolling back to 0. Then just compare the output of the counter with 49 999 999 and when the comparison is true enable a register (SR flip flop). When the CPU services the interrupt you would clear this same register so that you will be alerted by interrupt the next time the counter hits 49 999 999. This is practically how the timer peripheral in SOPC Builder and Qsys works.
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Altera_Forum
Honored Contributor II
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Since I'm in a good mood here is most of the logic minus the slave port decoding of the interrupt clearing (note: I just typed this really fast so there could be errors): 

 

input clear_interrupt; output wire interrupt; reg counter; reg interrupt_reg; wire set_interrupt_high; always @ (posedge clk or posedge reset) begin if (reset) begin counter <= 0; end else begin if (set_interrupt_high == 1) counter <= 0; else counter <= counter + 1'b1; end end always @ (posedge clk or posedge reset) begin if (reset) begin interrupt_reg <= 0; end else begin if (set_interrupt_high == 1) interrupt_reg <= 1; else if (clear_interrupt == 1) interrupt_reg <= 0; end end assign set_interrupt_high = (counter == 49999999); assign interrupt = interrupt_reg;
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