Hi,
Im using a DE0-board from terasIC. Quartus II 10.1 Web edition.
I've followed the "Nios II Hardware Development Tutorial" step by step and my first problem was encountered when I tried to:
"6. Verify that the Worst-case Slack values are positive numbers for Setup, Hold,
Recovery and Removal. If any of these values are negative, the design might not
operate properly in hardware. To meet timing, adjust Quartus II assignments to
optimize fitting, or reduce the oscillator frequency driving the FPGA."
altera_reserved_tck is -2.333 for both Worst-case Slack and Design Wide TNS.
The guidance tells me to optimize for fitting or reduce the oscillator frequency. I tried the first suggestion by:
Under the tab
physical synthesis optimizations:
Effort level: Extra
Optimize for fitting (.... density):
Both boxes checked.
Under the tab
fitter settings :
Fitter effort: Standard.
Well, still doesn't work. Did I optimize fitting the right way? How do I reduce the oscillator frequency?
I, for the sake of testing, tried to run as hardware after finish the last steps but Eclipse crashes at 57% complete all the time..
Merry Christmas,
mr_embedded
