Cordic core

[Altera_Forum]

hi im making a bit serial cordic in VHDL. i have written all the codes for the architecture but i cant figure out how to loop the architecture for n iterations. do i have to include a state machine?? can anyone help PLEASE........

[Altera_Forum]

Hi,  

  I am working Cordic coding in Verilog using MaxplusII software. I am facing the same problem as you too.. which is the iteration looping of the coding.     I've tried module instantiation and also genvar looping.. but it doesnt works either. If you have got a solution, I be happy if you can share it with me.. Thx alot

[Altera_Forum]

there is a Verilog CORDIC core in one of the Altera synthesis cookbooks. i ported it to VHDL for fun but i haven't run the simulation on the new code

[Altera_Forum]

Oh Hi.. thx for the reply. Well, I saw that cookbook rar file too. But i tried to run the code given using maxplus2.. unfortunately it doesnt sucessfully compile. there are some part that i dont wuite und the coding as well.  

 i) reg last_xshift,last_yshift; always @(posedge clk) begin  if (sclr) begin  last_xshift <= 1'b0;  last_yshift <= 1'b0;  end  else begin  last_yshift <= yshift;  last_xshift <= xshift;   end end   ii) // XYZ shift registers ////////////////////////////////// always @(posedge clk) begin  if (sclr) begin  x <= 0;  y <= 0;  z <= 0;  end  else begin  x <= {(isel ? xi : xsum),x[WIDTH-1:1]};  y <= {(isel ? yi : ysum),y[WIDTH-1:1]};  z <= {(isel ? zi : zsum),z[WIDTH-1:1]};  end end assign xshift = sign_ext ? last_xshift : x[round_num]; assign yshift = sign_ext ? last_yshift : y[round_num]; assign xo = x[0]; assign yo = y[0]; assign zo = z[0];   can u pls explain what is the function of these coding if u understand it..   on top of that, I am also curious about    1) for the iteration looping, are you using a finite state machine to control?  2) for the shifting.. is it an sign extended shifting? or simply jus right shifting.. with zero replacing the MSB ?   I really look forward for your reply and help. Thx in advance..

[Altera_Forum]

Did you read the code explanation in the pdf file? 

   --- Quote Start ---  unfortunately it doesnt sucessfully compile  --- Quote End ---   MaxplusII has limited HDL support. Why don't you change to Quartus?

[Altera_Forum]

--- Quote Start ---   1) for the iteration looping, are you using a finite state machine to control?  2) for the shifting.. is it an sign extended shifting? or simply jus right shifting.. with zero replacing the MSB ?  --- Quote End ---   1. you can use a register pipeline to propagate a 'valid' bit 2. if you have signed variables you use arithmetic shift, so you copy the MSB e.g. 1011 arithmetically shifted right becomes 1101

[Altera_Forum]

i tested the code in Quartus, it is synthesizable

[Altera_Forum]

Hi,  

  I been trying out my codes, in order to make sure if the code is functioning with the purpose of the coding. I would like to ask another question which is the input values.  Say the input bits are 16bits [15:0], then we know that in circular cordic, rotation mode is used to compute for sine and cosine. So, basically, xi=0.603, yi=0 and zi = input angle desired to calculate.   1) my question is - how to convert the input angle into binary format?  I saw some reference (input angle /360 ) x (2^16) and some ( input angle /180 ) x (2^16), so I am confused... which is the correct one?  On top of that, the answer would be in degree, what if I wan it to be in radian?   Do I convert ( input angle x pi ) / 180 first, then angle in radian / pi x 2^16 ?    2) When my set initial input xi =0.603 which is ( 1/ 1.646 ), and yi =0 , does it means that i do not have to divide with scale correction factor for the final answer, x(16) and y(16) anymore?   3) For the iterative cordic, every iteration looping passing the shifter, the number of bits shifted to the right depends on the internal iteration,n? case 1 : meaning at 1st iteration,x value is shifted one bit to the right, then the next looping, i=2, x value is shifted 2 bits to the rights, so on til i=15, x value is shifted 15bits to the right? Or,case2: every iteration loop, the x value is shifted only one bit to the right?    case 1 : signed_shifter x_shifter(iteration, x_i, x_i_shifted);  signed_shifter y_shifter(iteration, y_i, y_i_shifted);  for (j=0;j<i;j=j+1)  begin  x_1 <= x_i + y_i_shifted;  y_1 <= y_i - x_i_shifted;  end    case 2 : for (j=0;j<i;j=j+1)  begin  x_1 <= x - (y >> 1);   y_1 <= y + (x >> 1);   end   Pls help me out with this confusion, Thx alot. I appreciate your help very much.