Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Qsys 11.0sp1 DDR2 Uniphy generation problems under suse

Altera_Forum
Honored Contributor II
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I am using Quartus 11.0sp1 on Suse linux 11.4 (64bit), and try to generate a 

simple system with a nios processor, onchip memory and a ddr2 Uniphy 

controller in Qsys. 

The system generation works fine on a windows system but under linux I get the following error message: 

# ####### 

Info: c0: "ddr2ifc" instantiated altera_mem_if_nextgen_ddr2_controller "c0" 

Error: p0: add_fileset_file: No such file /tmp/alt5239_8498344429525475091.dir/0028_p0_gen/qsys/nios_ddr2ifc_p0_sequencer_rom.hex 

while executing 

"add_fileset_file $file_name [::alt_mem_if::util::hwtcl_utils::get_file_type $file_name 0] PATH $generated_file" 

("foreach" body line 4) 

invoked from within 

"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR2" $tmpdir SIM_VERILOG] { 

set file_name [file tail $generat..." 

("if" then script line 2) 

invoked from within 

"if {[string compare -nocase [get_parameter_value NIOS_SEQUENCER] "true"] == 0} { 

foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_seque..." 

(procedure "generate_verilog_sim" line 19) 

invoked from within 

"generate_verilog_sim nios_ddr2ifc_p0" 

Info: p0: "ddr2ifc" instantiated altera_mem_if_ddr2_phy "p0"# ####### 

 

Does anybody have any hints? 

 

Thanks
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Altera_Forum
Honored Contributor II
399 Views

Problem Solved! 

I had no "make" program on the new Suse installation!
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Altera_Forum
Honored Contributor II
399 Views

I am having the same problem under Ubuntu, and my "make" is installed already. Anyone has other hints on this? 

 

Thanks
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Altera_Forum
Honored Contributor II
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