Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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timing simulation vs real

Altera_Forum
Honored Contributor II
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Hello 

 

 

I am trying to compare a timing simulation (with specified pins) of a simple verilog XOR assignment in Quartus II to the actual timing on a Flex EPF10K70 device. That is to say, I am comparing a simulated v.s. real propagation delay between an input state change to output state change of the XOR function. 

 

I notice that the simulation shows a delay of approximately 27ns, but in hardware I see a consistent delay of only ~7.5ns for the same sequence (one input goes from low to high). 

 

Does anyone know why this might be? (Apologies: I am new to this) 

 

Thanks
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Altera_Forum
Honored Contributor II
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27 ns sound very unlikely for Flex10K.

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Altera_Forum
Honored Contributor II
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Yes, that is what I thought too. I cant see why it should be that slow, going by the datasheet, and obviously the real thing is not that slow. I can make it simulate slightly faster by automatically selecting input/output pins but this yields a simulated 5ns improvement only (still >20ns for such a simple assignment). 

 

I tried repeating the experiment using an EPM3032ATC44-4 (4ns). Both the timing simulation and real device timing agree pretty well and both match the performance that I would expect. 

 

So is there maybe a setting somewhere for the FLEX device that I am missing? This is an early version of quartus II (v4).
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Yes, that is what I thought too. I cant see why it should be that slow, going by the datasheet, and obviously the real thing is not that slow. I can make it simulate slightly faster by automatically selecting input/output pins but this yields a simulated 5ns improvement only (still >20ns for such a simple assignment). 

 

I tried repeating the experiment using an EPM3032ATC44-4 (4ns). Both the timing simulation and real device timing agree pretty well and both match the performance that I would expect. 

 

So is there maybe a setting somewhere for the FLEX device that I am missing? This is an early version of quartus II (v4). 

--- Quote End ---  

 

 

Hi, 

 

what are the results of the timing analysis ?  

 

Kind regards 

 

GPK
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