JTAG - Incorrect clock value

[Altera_Forum]

I am using Quartus II ver. 10.1 build 153, with MAX II Development board and EPM3128ATC100-10 

 I am getting errors and am unable to erase/program my target board. The Development board programs fine, just not my target board. I have checked the signal lines and they ring out. Originally my prototype board had TDI connected to pin 7 of the JTAG header but since corrected to pin 9.  The Programmer gave error message "can't connect to jtag chain  In Chain debugger Chain Integret gives message "No device detected"; Chain Debugging gives message Incorrect clock value.  I've attached a screen shot of logic analyzer when attempt erase of my prototype board.  Any suggestions?

[Altera_Forum]

The shown JTAG waveform would reset the TAP controller to RUN_TEST/IDLE and leave TDO tri-stated. It doesn't look like any usual Quartus programmer sequence.

[Altera_Forum]

I don't know how the programmer sequence would have changed. I didn't make any changes to the programmer set up and I can program the development board without problems but not the target board. 

 I have noticed that when I compile a project for the development board using an EPM1270F256C5 it produces CFM and UFM files in the .pof When I compile a project for the EPM3128ATC100-10 it does not produce these files in the .pof  I've checked the JTAG lines and in desperation replaced the EPM3128 but still get "can't access JTAG chain" when I try to program the target board.