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Gray Code

Altera_Forum
Honored Contributor II
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Hi, 

 

I am a student, and my assignment is to create a gray code to bargraph design in VHDL using select signal assignment. 

 

I have been toying around with the following code, but it just doesnt seem to work. 

 

library IEEE; use IEEE.STD_LOGIC_1164.all; entity gray_2_bar is port( gray : in std_logic_vector (3 downto 0); bar_graph : out std_logic_vector (9 downto 0)); attribute loc : string; attribute loc of gray: signal is "P2,P3,P4,P5"; attribute loc of bar_graph: signal is "P27,P26,P25,P24,P23,P21,P20,P19,P18,P17"; end gray_2_bar; --}} End of automatically maintained section architecture gray2bar1 of gray_2_bar is signal temp: std_logic_vector (3 downto 0); begin temp <= gray; with temp select bar_graph <= '0' when "0000", <= '1' when "0001", --I am getting error on this line. <= '2' when "0011", <= '3' when "0010", <= '4' when "0110", <= '5' when "0111", <= '6' when "0101", <= '7' when "0100", <= '8' when "1100", <= '9' when "1101"; end gray2bar1; The error is as follows:  

# Error: COMP96_0015: gray_2_bar.vhd : (46, 3): ';' expected.# Error: COMP96_0019: gray_2_bar.vhd : (46, 3): Keyword "end" expected.# Error: COMP96_0016: gray_2_bar.vhd : (46, 6): Design unit declaration expected. 

 

 

Any help would be greatly appreciated. 

 

Thanks and Best Regards 

Sarovar C
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Altera_Forum
Honored Contributor II
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Ok well still working on it, here is ver. 2 of the code: 

 

library IEEE; use IEEE.STD_LOGIC_1164.all; entity gray_2_bar is port( gray : in std_logic_vector (3 downto 0); bar_graph : out std_logic_vector (9 downto 0)); attribute loc : string; attribute loc of gray: signal is "P2,P3,P4,P5"; attribute loc of bar_graph: signal is "P27,P26,P25,P24,P23,P21,P20,P19,P18,P17"; end gray_2_bar; --}} End of automatically maintained section architecture gray2bar1 of gray_2_bar is signal temp: std_logic_vector (3 downto 0); begin temp <= gray; with temp select bar_graph <= "1111111110" when "0000", <= "1111111100" when "0001", --Still the same error on the same line. <= "1111111000" when "0011", <= "1111110000" when "0010", <= "1111100000" when "0110", <= "1111000000" when "0111", <= "1110000000" when "0101", <= "1100000000" when "0100", <= "1000000000" when "1100", <= "0000000000" when "1101", <= "0000000000" when others; end gray2bar1;
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Altera_Forum
Honored Contributor II
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Just wanted to post that I managed to figure it out

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