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i have transfer the block symbol file to the verilog using quartus,but i simulate it in the modelsim,it has the wrong answer.
this is the block file of a three ffs. http://www.alteraforum.com/forum/attachment.php?attachmentid=3780&stc=1&d=1299584679 the is the modelsim result, http://www.alteraforum.com/forum/attachment.php?attachmentid=3779&stc=1&d=1299584679 but when i write the verilog myself ,i get the right answer,so what's wrong with the Modelsim,any ideas? Many thanks!Link Copied
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are you converting the .bdf to Verilog? can you post the converted Verilog?
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