I have a 250M sample rate ADC ( AD9481 , two 8 bit output channels) connect to cyclone II EP2C8Q208C8 , two of their pins ( DCO+ and DCO-, their clock is 60M) are differential output are connect to differential inputs of EP2C8Q208C8 . When dco+ is raising edge channel 1 data is valid while dco- is raising edge channel 2 data is valid. Under the code below :
module mux3(dco+,dco-,data1,data2,data3);
input dco+,dco-;
input [7:0] data1;
input [7:0] data2;
output [7:0] data3;
reg [7:0] data3;
reg sela;
reg selb;
reg [7:0] data_a;
reg [7:0] data_b;
initial begin
sela = 1'b0;
selb = 1'b0;
end
always @ (posedge dco+) begin
sela <= ~ selb; // warning, must meet setup/hold
data_a <= data1;
end
always @ (posedge dco-) begin
selb <= sela; // warning, must meet setup/hold
data_b <= data2;
end
always @ (sela, selb, data_a, data_b) begin
if (sela^selb) begin
data3 = data_a; // warning, combinatorial output.
end else begin
data3 = data_b; // warning, combinatorial output.
end
end
endmodule
The question I ask is can the code above function properly as two channels are multiplex and only one channel is selected as output ????
