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hello, i am having problem writing and reading into SRAM on de2 board. the model of my SRAM is IS61LV25616 512KB. following is part of my code:
--- Quote Start --- # define loop 125000 src_ptr = EXT_SRAM_BASE; dest_ptr = EXT_SRAM_BASE; for(i=0;i<loop;i++) { IOWR(src_ptr, i, i); } for(i=0;i<loop;i++) { printf("Data at %X is %d\n", dest_ptr, IORD(src_ptr, i)); dest_ptr++; } --- Quote End --- when i write 0=9 into sram, it works fine. when i write 0-125000, suppose the data at 1st address of SRAM is 0 but it appears to be 65536 then continue until 124999. why it doesnt start with 0 to 124999? is there anything to do with the timing of the sram? i editted my sram from tcl file as in attachment. i am not sure it has problem with my code or sram. pls help.Link Copied
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You can use the memory test template to check the SRAM and your timing parameters.
Are you sure the SRAM isn't used for anything else? Program code, heap/stack memory, or exceptions?- Mark as New
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Hi, I am using flash memory in my project and i did not configure it in SOPC. is it ok to use memtest software? yes, i am sure because program code, heap/stack and exception including reset vector are set to SDRAM.
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Besides, if possible, I need help with DMA too. I have lost idea of how to debug anymore. My DMA Controller setting in SOPC is Width of the DMA Register Length is set to 32bit and the rest is left at default. However, my system stucks (infinite loop) at
while (!txrx_done); printf ("Transfer successful!\n"); I dont know why. i just follow the code exactly without editing anything.. but the creator can run it but i cant. i dont know what's the prob, i tried msg in the thread but no one replies. my code (taken from one of the threads in the forum) --- Quote Start --- # include <stdio.h># include <stdlib.h># include <stddef.h># include <string.h> # include <system.h># include <io.h> # include <alt_types.h># include "sys/alt_dma.h"# include "sys/alt_cache.h"# include "sys/alt_alarm.h"# include "alt_types.h" static volatile int txrx_done = 0; //callback function when DMA transfer done static void txrxDone(void * handle, void * data) { txrx_done = 1; } void initMEM(int base_addr,int len) { for (int i=0;i<len;i++) { IOWR_8DIRECT(base_addr,i,i); } } int main() { printf("testing ssram & sdram : dma operation\n"); alt_16 buffer[10]; //memset((void *)SSRAM_0_BASE,0x7a,0x10);//this write base on byte initMEM(SDRAM_1_BASE,0x10); memset((void *)(SDRAM_1_BASE+0x10),0x33,0x10); printf("content of sdram_1:before DMA operation\n"); for (int i=0;i<0x10;i++) { printf("%d: %x\n",i,IORD_8DIRECT(SDRAM_1_BASE,i)); } printf("content of sdram_1(offset 0x10):before DMA operation\n"); for (int i=0;i<0x10;i++) { printf("%d: %x\n",i,IORD_8DIRECT(SDRAM_1_BASE+0x10,i)); } int rc; //request alt_dma_txchan txchan; alt_dma_rxchan rxchan; void* tx_data = (void*)SDRAM_1_BASE; /* pointer to data to send */ void* rx_buffer = (void*)(SDRAM_1_BASE+0x10); /* pointer to rx buffer */ /* Create the transmit channel */ if ((txchan = alt_dma_txchan_open("/dev/dma_0")) == NULL) { printf ("Failed to open transmit channel\n"); exit (1); } /* Create the receive channel */ if ((rxchan = alt_dma_rxchan_open("/dev/dma_0")) == NULL) { printf ("Failed to open receive channel\n"); exit (1); } /* Post the transmit request */ if ((rc = alt_dma_txchan_send (txchan, tx_data, 0x10, NULL, NULL)) < 0) { printf ("Failed to post transmit request, reason = %i\n", rc); //exit (1); } /* Post the receive request */ if ((rc = alt_dma_rxchan_prepare (rxchan, rx_buffer, 0x10, txrxDone, NULL)) < 0) { printf ("Failed to post read request, reason = %i\n", rc); //exit (1); } /* wait for transfer to complete */ while (!txrx_done); printf ("Transfer successful!\n"); printf("content of sdram_1:after DMA operation\n"); for (int i=0;i<0x10;i++) { printf("%d: %x\n",i,IORD_8DIRECT(SDRAM_1_BASE,i)); } printf("content of sdram_1(offset 0x10):after DMA operation\n"); for (int i=0;i<0x10;i++) { printf("%d: %x\n",i,IORD_8DIRECT(SDRAM_1_BASE+0x10,i)); } return 0; } --- Quote End ---
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