Timing of RAM

[Altera_Forum]

I use Simple Dual-port memory as a FIFO.  

The attachment is Simple Dual-Port Timing Waveforms in Altera's handbook. It seems the address changes on the negative edge of clock. This makes my design rather complicated. Can I change address on the posetive edge of clk?

[Altera_Forum]

It only looks that the address changes on the falling edge. The waveforms have been drawn to emphasize maximum setup and hold times in regard with the positive edge of the clocks, but all changes occur on the rising clock edges.

[Altera_Forum]

I think it may just be confusion. The memory latches the address when the clock goes positive, and if you trigger the address source reg on the positive edge, it really means that the reg input is captured during the positive clock and is actually launched at the end of the clock. Therefore your design is probably OK. To be sure, I suggest do a functional then a timing simulation of just a dff reg as ram address and look at the ram output. 

A hint: be sure to connect ALL the ram inputs to avoid a wysiwyg error and use output pins on the ram qa port so synthesis won't throw it away. The functional sim will show everything happening on the leading edge, but the timing will show the true waveform.