DDR Interface SDC Constraint

[Altera_Forum]

Hi. 

  I have written a constraint on DDR interface. When I run timing analysis, it shows that it fail in setup time. Based on the ddr example I have seen, it runs at 400MHz. So, my ddr shouldn’t fail because it runs at slower speed which is 125MHz. So, there should have some mistake in my sdc constraint. I have attached the sdc file, timing quest report, overview of ddr tx interface.  Please have a look on the sdc and correct me if I constraint not properly.    FYI, the interface is of RGMII(Triple Speed Ethernet) and device is stratix iv gx.      Thanks

[Altera_Forum]

Does TQ give you any warnings (besides obvious "critical warning:timing requirements not met)?

[Altera_Forum]

I can not read your sdc.txt because I'm sitting behind a firewall/gateway blocking that. 

But I have the idea that you are driving the transmit clock directly from the PLL (that is what your schematic shows). This can never meet timing because it takes the data quite some time arriving at the pin. May I suggest you to drive the tx clock out with a DDROUT block as well. In your sdc create a generated clock for this pin and use this as the clock in your set_output_delay constraints for the data outputs.

[Altera_Forum]

--- Quote Start ---  Does TQ give you any warnings (besides obvious "critical warning:timing requirements not met)?  --- Quote End ---    There is no other warning given by TQ.      --- Quote Start ---    Your refer to clock or data? Can you explain it more details?  Thanks

[Altera_Forum]

--- Quote Start ---  Your refer to clock or data? Can you explain it more details?   --- Quote End ---   I deduced from your drawing that the 90degree tx clock is a direct pll output onto a dedicated pin. This has little delay from source (pll) to output (pin). (Even more, if you compensated the PLL to this output pin the delay is virtually 0). But the data goes through a combinatorial multiplexer and thus sees more delay before it reaches the pin. That's why I suggested to drive the tx clock using a DDROUT as well. Then the 90 degree output clock incurs 'identical' delays as incurred by the data.

[Altera_Forum]

I added a TQ report image to compare with.