Opinion about sgdma design in sopc needed

[Altera_Forum]

Hey, 

 i am working at my 2nd nios design now and have following situation:  i have a 32-bit input bus, clocked with around 1 MHz and a Nios with 42 MHz running on sdram. Now i thought of sending the input data over dma into the sram so that afterwards the nios can work with it. I've done that already with an analog dev dsp once, not with nios :/  As i already have a 32-bit pio i thought of using this one for the input data.  I now thought of the sopc design attached in this post as a solution that will transfer me as much data as specified by nios from the pio to the sram, clocked with the 1 MHz clock.  But i am pritty unsure if this could work or how the design should be so that it works, esp. the connections in the sopc builder and the two different clock areas...  And so i hope to get some feedback from here ^^  Thx in advance, haqim.

[Altera_Forum]

The sopc builder will add a clock crossing bridge when an avalon master-slave pair are running from different clocks. 

The presence of these bridges (and the bus width adapters) doesn't seem to be indicated in any useful way.

[Altera_Forum]

If you manually insert clock crossing bridges you'll get higher throughput. The clock crossing adapters that are inserted behind the scenes if you have a master and slave pair on different clock domains are not pipelined so they don't have a throughput of data every clock cycle. 

 As a result I recommend keeping the SGDMA on the 42MHz domain, placing the PIO on the 1MHz domain and place a clock crossing bridge between the SGDMA master and PIO slave port. It sounds like you are using 1MHz to get a fixed data rate off-chip so you always want to make sure the source of the data (memory and DMA) operate faster to prevent underflow.