HPC-II for DDR2

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

HPC-II for DDR2

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hi all !

I'm studying about HPC-II for DDR2 with half-rate mode of CycloneIV-GX, i used Megafunction to create it, with features : local bus = 128bits, mem_clk = 166.667Mhz, col addr = 10bits, row addr = 13bits, bank addr = 2bits, DQ = 32bit, DQS = 4bit, BL = 8beats, burst ordering : sequential, CAS = 3, local-to-memory address mapping : chip-row-bank-col, command queue : 8, local maximum burst count : 4, controller latency : 5, skip calibration for simulation.

then i simulate, when i issue read-command with local_size = 4, i see data from DDR2 memory like with data that i wrote, but at local interface of HPC-II, data don't expected, local_rdata_valid and local_rdata[127:0] signals are not match, please watch picture that i attached.

Did i miss features when create HPC-II,...

Thanks all.

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