Transceiver Pseudo-CML equivalent circuit?

[Altera_Forum]

I'm currently testing with the Stratix IV GX development kit and would like to know if anyone has details on the equivalent circuit for the transmitter. 

 A CML driver typically consists of a differential pair terminated in 50-ohms to a termination voltage, a current sink, and current steering logic, as shown on p9 of this data sheet  http://www.analog.com/static/imported-files/data_sheets/adcmp572_573.pdf  (nothing special about this part, it just had a CML driver circuit diagram).  The CML transmitter outputs high and low voltages by steering current through one of the differential signals, i.e., in the data sheet above, one of the transistors is on, while the other is off.  The Stratix IV handbook has the circuit diagram for a DC coupled link between a Stratix IV GX transmitter and receiver on p1-45 of Volume 2 (p489 of the PDF).  http://www.altera.com/literature/hb/stratix-iv/stratix4_handbook.pdf  However, this diagram does not show how the transmitter buffer is implemented.  If I assume that the buffer sinks current according to the CML driver circuit in the Analog Devices data sheet above, then I can draw an equivalent circuit in LTSpice to calculate the DC currents and voltages (yeah, I can do the same with a piece of paper and a calculator too). For a transmit termination voltage of 0.65V and receiver termination voltage of 0.82V, the result is a logic high voltage of 735mV and a logic low of 435mV, assuming 50-ohm terminations and a transmitter current sink of 12mA (the transmitter Vod setting can be used to adjust this).  The problem is that I observe a logic high of 910mV and a logic low of 540mV. The fact that the observed logic high is greater than 735mV, means that the receiver termination resistor is actually sinking ~2mA (to develop ~100mV across it), meaning the driver is sourcing ~2mA current.  This is inconsistent with the CML driver circuit. However, perhaps that is the meaning of pseudo in pseudo-CML :)  Anyone have any insight into this?  Cheers, Dave

[Altera_Forum]

The other interesting thing that I observe, is that if I change VOD, I change the voltage swing, but not the common mode voltage, ie., 

 1. VOD = 3 (default), Vhigh = 910mV, Vlow = 540mV, so Vcm = 725mV and Vpp = 370mV  2. VOD = 0, Vhigh = 800mV, Vlow = 660mV, so Vcm = 730mV and Vpp = 140mV  3. VOD = 7, Vhigh = 1100mV, Vlow = 330mV, so Vcm = 715mV and Vpp =770mV  So the common mode voltage is essentially unchanged.  If the transmitter was really only able to sink current, then as the sink current is increased, the Vlow voltage should get further from the Vhigh voltage, and the common-mode point should move lower. The observations show that changing VOD increases the peak-to-peak voltage, without changing the common mode voltage. Hence, the transmit buffer is not a simple CML source.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Hence, the transmit buffer is not a simple CML source.  --- Quote End ---   Yes. What made you think, it would use unipolar current sources? It's not stated in the Altera documentation at any place.  The Altera documentation is suggesting a (differential) bipolar current source with programmable resistive termination. But I guess, you won't find implementation details. As with other FPGA OCT variants, there are most likely no physical resistors, just transistors. It's also not clear, if the PCML driver uses real current sources.   All you can rely on is the output voltage specification in the datasheet.  P.S.: Altera has filed patents related to FPGA IO structures. Particularly US2006220681 "Methods and Apparatus to DC Couple LVDS Driver to CML Level" may be interesting. US7855577 "Using a Single Buffer for Multiple I/O Standards" is also related to the topic. A good place to search for patents and get the full text http://worldwide.espacenet.com

[Altera_Forum]

Hi FvM, 

   --- Quote Start ---  What made you think, it would use unipolar current sources?    --- Quote End ---  Nothing really, I was just stating that the naive interpretation of Pseudo-CML driver as being like a CML driver was not correct, so was interested in a more correct definition :)    --- Quote Start ---   It's not stated in the Altera documentation at any place.   --- Quote End ---  Yeah, I guess we can't expect it, since its part of Altera's secret recipe.    --- Quote Start ---   The Altera documentation is suggesting a (differential) bipolar current source with programmable resistive termination. But I guess, you won't find implementation details. As with other FPGA OCT variants, there are most likely no physical resistors, just transistors. It's also not clear, if the PCML driver uses real current sources.    --- Quote End ---  That was the impression I was getting. I thought it confusing that the voltage between resistors was referred to as a common-mode voltage, when in fact its really a termination voltage. None of the signal measurements have a common mode equal to either the transmit Vcm or receive Vcm; unless of course I put a DC block in the signal path.    --- Quote Start ---    All you can rely on is the output voltage specification in the datasheet.   --- Quote End ---  But even that is ambiguous. The termination voltages at the receiver are 820mV or 1100mV. There are comments in the DC switching characteristics chapter regarding the allowed common mode voltage as being within 10% of these values. However, from the measurements of the common mode voltages and peak-to-peak swings, these specifications are being violated by a GX-to-GX link, eg., Vcm ~ 730mV in all cases.  Table 1-23 on p1098 has the receiver characteristics. That table indicates that a voltage swing of 100mV would be an ok signal, but the common move appears to be limited to within 10% of the termination voltage. There are no comments on the sink/source current maximums for the transceiver pins.   I'm interested in whether the common mode can be shifted, and what the maximum currents are, as I have a PCML driver that is referenced to ground. A DC connection would result in current being sourced from the receiver, and the common mode shifting down. I can test an AC connection with this particular part (it has a PRBS spreader option), but I also want to investigate whether a DC connection is possible.     --- Quote Start ---    P.S.: Altera has filed patents related to FPGA IO structures. Particularly US2006220681 "Methods and Apparatus to DC Couple LVDS Driver to CML Level" may be interesting. US7855577 "Using a Single Buffer for Multiple I/O Standards" is also related to the topic. A good place to search for patents and get the full text http://worldwide.espacenet.com  --- Quote End ---  Ah-ha! Secret recipe ingredients. I'll check them out thanks!  Thanks for responding to this question.  Cheers, Dave

[Altera_Forum]

Hi FvM, 

 US7924046 "Configurable emphasis for high-speed transmitter driver circuitry" describes transmitter circuits that are possibly the ones used in the Stratix devices. The transmit pre-emphasis circuits require current sources and sinks.  This helps me understand the operation of the transmitter.  Cheers, Dave

[Altera_Forum]

Just to follow-up on the transmitter side of this discussion, the attached LTSpice circuit shows how two current sources at the transmitter can be used to get signal high/low voltages pretty close to those measured for the VOD default setting of 3, i.e., with 7.5mA current source, Vhigh = 920mV, Vlow = 550mV. 

 Cheers, Dave

[Altera_Forum]

Hello Dave,  

 interesting. You see, that I didn't scan for all related Altera patents, I found I/O driver the stuff when looking for something different. The current switching topology refers to the standard design for LVDS drivers. It typically has no termination voltage source but a common mode voltage control loop, see the below schematic. You would be able to identify the actual implementation by dynamical measurements, because the common mode control loop would show a reduced bandwidth.  On the other hand, the schematic is still a simplification, because it has no programmable termination resistors.   Regards, Frank

[Altera_Forum]

Hi Frank, 

   --- Quote Start ---    I didn't scan for all related Altera patents   --- Quote End ---  No, I didn't think you had, but figured you might be interested in the patent I ended up finding.   Thanks for the hint to look at patents, I'll have to remember that in the future.    --- Quote Start ---    I found I/O driver the stuff when looking for something different.    --- Quote End ---  I also found lots of other patents that will distract me from doing real work :)    --- Quote Start ---    The current switching topology refers to the standard design for LVDS drivers. It typically has no termination voltage source but a common mode voltage control loop, see the below schematic. You would be able to identify the actual implementation by dynamical measurements, because the common mode control loop would show a reduced bandwidth.  On the other hand, the schematic is still a simplification, because it has no programmable termination resistors.    --- Quote End ---  Thanks. I'm happy with my simplified understanding of the transmitters now.  You don't happen to have any insight into the receiver common mode voltage range, and the current source capabilities of the receivers do you?  Cheers, Dave

[Altera_Forum]

Hello Dave, 

 I must admit, that I've only limited experience with Altera gigabit transceivers. I did a PCIe customer project, but I'm more familiar with sub-gigabit LVDS interfaces. I try to keep informed about available technologies, however.  I notice, that utilizable receiver common mode voltages are speed dependant, you get optimal performance in a smaller range. Furthermore, they are affected by P,V,T variations. In so far, you can't but rely on specifications.  Regards, Frank

[Altera_Forum]

Hi Frank, 

   --- Quote Start ---   I must admit, that I've only limited experience with Altera gigabit transceivers. I did a PCIe customer project, but I'm more familiar with sub-gigabit LVDS interfaces. I try to keep informed about available technologies, however.   --- Quote End ---  Same here. My last design made a lot of use of the LVDS transceivers, but the FPGAs did not have the GXB blocks.    --- Quote Start ---   I notice, that utilizable receiver common mode voltages are speed dependant, you get optimal performance in a smaller range. Furthermore, they are affected by P,V,T variations. In so far, you can't but rely on specifications.   --- Quote End ---  Where do you see that information? In the Stratix IV handbook, the only switching information I see is the stuff in Table 1-23 on pages 1096 to 1104 of the PDF. p1098 has the receiver details. Nothing in there about common mode changes that are speed dependent. The Stratix IV devices have a "Receiver buffer and CDR offset cancellation" mode where they should take care of PVT changes. I suspect if I try a DC connection where I draw too much current from the receivers, that this stuff won't work properly. I'm not planning on trying it, as I do not want to damage the FPGA.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---   I suspect if I try a DC connection where I draw too much current from the receivers, that this stuff won't work properly. I'm not planning on trying it, as I do not want to damage the FPGA.   --- Quote End ---    Thank you for all your disscusion on this issue. Based on your experiment results and your helpful replies, I also draw some schematic and did simulaion using PSPICE, and now I have the same opion with you that the Transimitter output buffer is constructed similar to LVDS buffer, for both of them are sourcing differential current throught both of the differential pins at the same time. But I really want to know the maxium sink/source current capability of transimit termination resistors, because I want to terminate the transimit signals using standard 1.5-V CML termination method at the receiver end (the receiver is a programmable delay chip), which will give about a maxium of 12mA sink current through the internal termination resister in ArriaII GX. I really would like to know whether this 12mA current will damage the output buffer of transimitter in FPGA?  Thank you!  Dajun Huang

[Altera_Forum]

Hi Dajun, 

   --- Quote Start ---   But I really want to know the maxium sink/source current capability of transimit termination resistors, because I want to terminate the transimit signals using standard 1.5-V CML termination method at the receiver end (the receiver is a programmable delay chip), which will give about a maxium of 12mA sink current through the internal termination resister in ArriaII GX. I really would like to know whether this 12mA current will damage the output buffer of transimitter in FPGA?   --- Quote End ---  I don't know the answer to this. How about you submit a service request to Altera directly, and then post their response here? That would be very helpful.  Cheers, Dave