FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6343 Discussions

DVI input and DVI output

Altera_Forum
Honored Contributor II
987 Views

Hi, 

 

I have the problem that I am using Altera cyclone III EPC3C120 Development board.The design example requires an Bitec HSMC Quad Video input daughter card. But I don't have it.Instead I am planning to use the Bitec HSMC DVI input/output daughter card for input and output. 

 

Can anyone help me with a sample design with DVI input and DVI output? 

 

Sneha
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
247 Views
0 Kudos
Altera_Forum
Honored Contributor II
247 Views

Hi, 

 

I tried to run the code suggested by you but I am getting some errors.It is from the design example from http://www.bitec.ltd.uk/hsmc_dvi.html 

 

DVI 1080P Loop-through CIV  

This sof updates the EDID EEPROM on the HSMC DVI board to correctly report 1080P@60 

 

They are 

 

Error: Node instance "auto_inst" instantiates undefined entity "alt_vip_vfb_0_GN" 

Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 802 warnings 

Error: Peak virtual memory: 346 megabytes 

Error: Processing ended: Mon Apr 04 11:12:36 2011 

Error: Elapsed time: 00:00:18 

Error: Total CPU time (on all processors): 00:00:22 

 

Help please.. 

 

Rgds 

 

Sneha
0 Kudos
Altera_Forum
Honored Contributor II
247 Views

Hi, 

 

I also tried to run the design HSMC DVI 1080P SDRAM Loop-through Reference Design 

 

But I am facing these errors: 

 

Error: Node instance "auto_inst" instantiates undefined entity "my_alt_vip_vfb_top_GN" 

Error: Node instance "auto_inst" instantiates undefined entity "my_alt_vip_vfb_bot_GN" 

 

Can anyone explain what these errors mean?
0 Kudos
Reply