Using assert() report in VHDL

[Altera_Forum]

Hello! 

 I'm trying to use command assert(...) report "..." in Quartus 9.1 to debug my project. I've tested different combinations of this command according to the literature in the Internet, but cannot see my report message anywhere.  Should I check some options in Quartus or where exactly this message should appear?  P.S. I'm using standard simulation tool.  Thanks!

[Altera_Forum]

Try this in your code somewhere: 

 process begin  wait for 10 us;  assert false  report "Simulation complete!"  severity failure; end process;  This process will end your simulation after 10 us. See if the message shows up somewhere. If not, try to learn to use Modelsim. Its a much nicer simulation tool.  Cheers, Dave

[Altera_Forum]

Are you sure you're using assert correctly. it only does the report if the thing inside the brackets is false. I remember it by: 

 assert all_is_good report "Something went wrong" severity failure;

[Altera_Forum]

Thank you for your answers! 

 Would you say, where this message should appear? Quartus main window tabs? Simulation window or like pop-up message?

[Altera_Forum]

I would look in the log messages. Since the example I gave you should terminate the simulation, you may even get a pop-up. Its quite possible that the Quartus simulator ignores these though. So like I said, learn to use Modelsim and you will be much happier. 

 Cheers, Dave

[Altera_Forum]

In Verilog, the assert messages only started to appear with Quartus 10.0. 

Maybe try to update ?