epcs initialization hangs in an endless loop.

[Altera_Forum]

Hello. 

 I am building a Nios2 system on a Cyclone4E EP4CE30F23 using Quartus 9.1sp2.  I have instantiated an epcs controller in sopc builder so that I can write to my configuration device. I specified that the controller should use the dedicated AS interface.  My problem is that when the HAL initializes the epcs controller, it ultimately hangs in an endless loop because the epcs SPI port is not indicating that an SPI transmit completed.  The stack trace is _start() alt_main() alt_sys_init() alt_epcs_flash_init() alt_epcs_flash_query() epcs_read_electronic_signature() alt_avalon_spi_command()  The loop is in alt_avalon_spi_command() is as follows:  do {  status = IORD_ALTERA_AVALON_SPI_STATUS(base); } while (((status & ALTERA_AVALON_SPI_STATUS_TRDY_MSK) == 0 || credits == 0) && (status & ALTERA_AVALON_SPI_STATUS_RRDY_MSK) == 0);  Any help with this would be greatly appreciated.  Thank you Scott Wild

[Altera_Forum]

I Found it! 

 The EPCS's 0x800 byte address space consists of a 0x400 byte ROM in the lower half and an SPI controller in the upper half.  For some reason, the BSP generates the line:  EPCS_FLASH_CONTROLLER_0_REGISTER_OFFSET 512 in system.h.  The correct value should be 1024 since the SPI registers begin after the end of the 0x400 byte ROM.  This error ultimately causes an incorrect base address to be passed into alt_avalon_spi_command(base).  Once I changed the line to:  EPCS_FLASH_CONTROLLER_0_REGISTER_OFFSET 1024 everything works fine.

[Altera_Forum]

The boot loader rom was 512 in older families, Cyclone and CII. 

Maybe BSP V9.1 recognizes only CIII and assumes your CIV is a old device.

[Altera_Forum]

This issue had been resolved in Quartus II v10.0 

 Cheers, Caridee

[Altera_Forum]

Thank you for the additional info.

[Altera_Forum]

Thank you, I met the same problem and resolved it by above way.