fft on nios

[Altera_Forum]

hello everyone. 

 im working on speech recognition project using nios2 on de2 board. now i need to do fft to the signals i get from the audio codec. can anyone help with this ? how to conect the fft core to the nios ? and if anyone have examle i will be very greatful if he can send it to me.   thanks

[Altera_Forum]

Most people use DMAs for this. So they put a block of data into memory and feed it into the FFT block by performing memory to streaming transfers. The output of the FFT block is then streamed back to memory using a DMA. 

 The reason for using DMAs is that if you are using dedicated hardware for the FFT calculation then you don't want a relatively slow processor in the data path. The DMA can handle moving a word of data every clock cycle which is a closer match to the FFT hardware throughput capabilities.

[Altera_Forum]

first of all tanks allot. 

 i will be gratful if you can send me some example of how to do it. and i also want to know if i do it only with sopc or i shold writr vhdl code that connect th fft to the nios ( i am new in this buisnes).   and tanks again

[Altera_Forum]

Sorry I don't have any examples of wiring up the FFT core to an SOPC Builder system but it should be fairly straight forward to do using component editor in SOPC Builder. You might need to include some wrapper logic around the FFT core. 

 Do you need to perform the FFT at high speeds or can you use a software based FFT? If you need to use hardware I would expect the following data flow:  Codec --> DMA --> FFT --> DMA --> Memory  Using a pair of DMAs would be easiest but you could get away with using a single DMA assuming there is enough buffering present in the FFT to support this.

[Altera_Forum]

tanks agin. 

 first of all i do speech recognition project and i sample at 8Khz, so it is not so fast. second thing when you say codec do you meen the audio codec? because if yuo do meen it i alredy build the project with the audio ip core so i control the codec by software, can i control the dma with software?   and last thing is i dont know what do you meen when you say "wrapper logic" .

[Altera_Forum]

I would expect the audio codec to have either a ST source port that streams data out of it or a MM slave port that can be read by a master. If the data is only 8kHz coming in then you could probably do this entire project in C code running on the processor (including the FFT). 

 With DMA engines you typically control them using software which tells it the type of data transfer to perform. For example in your case transferring data from the codec to memory would be the type of thing the software would do to inform the DMA what to do. If you implement everything in software then you may not need a DMA though. For example if the code has an interrupt line you could use that to have the CPU read the next value out of it and the rest of the time the CPU is doing the signal processing (FFT). That would be a good first step and if that is not able to keep up then you can switch to using hardware acceleration (DMAs and/or dedicated FFT hardware).

[Altera_Forum]

I'm not sure I'd want to take interrupts at 8kHz - not through any generic interrupt handler code. 

Using a fifo to buffer enough samples for 1 fft would probably be enough. We are using the hardware fft with dma to feed data in/out to do tone detect on 240 8kHz TDM streams. With dma and the hardware fft this isn't a timing constraint.

[Altera_Forum]

I agree, pulling samples out of a FIFO would be a much better approach. Haraim, if your audio interface does not have buffering built in I would recommend adding it. A common approach is to set a fill level on the FIFO that you use to alert the CPU that you have a block of data ready to go (FFT input size in your case).

[Altera_Forum]

the all system is alredy built exept the fft. 

i read the data from the codec by the audio ip core. all the samples is stored in the sram and i want to send the samples from the sram to the fft. is it posible? if i have a good c code of fft i would use it. and one more question, what will be the best paremetes for the fft core with 1024*8 real samples, fixed point of 24 bit eache.

[Altera_Forum]

With a hardware based FFT you would normally use a DMA to move the samples from the SRAM into the FFT and then back out to memory. With a software implementation you would just have the software access the data directly. 

 In this zip file is a file called sw_only_fft.c which is a radix 2 FFT that can be run on Nios II: http://www.altera.com/literature/tt/c2h_tutorial.zip It by no means is optimized but if you google search around you'll find it's very similar to other code fragments floating around out there. If you study the code you'll find out how many operations are performed per block of input data which should give you a rough idea how long it'll take to run on a Nios II core.

[Altera_Forum]

hey 

 i try torun this example but i have problam with it. if i run the hardware fft wich kind of the streaming will be best for me?

[Altera_Forum]

I would just run the software portion of the design to learn more about the FFT algorithm. The hardware version in this design requires the use of the Nios II C2H compiler and it uses MM accesses for both the input/output as well as the twiddle factor look ups. The hardware version is optimized for the C2H accelerator so I wouldn't recommend trying to learn from it.

[Altera_Forum]

hi 

can you tell me how to run the codec under nios