Timing error when storing result in RAM blocks using In-System Memory Editor

[Altera_Forum]

Hi, 

 My design consists of some mathematical calculations (multiplications, additions,...). I supply the input using a RAM block and am trying to store the output using another RAM block. I use the In-System Memory Editor to read my output result.   Upon compiling my design, I got Critical Warnings stating 'timing requirements are no met'. I figured this is due to propagation delay between the input and output storage, since I am using the same clock for both, and I added a second clock for the output RAM block.   Re-compiling gave me the same timing error. So I opened up the TimeQuest Network Analyzer, went to 'Report Top Failing Paths' and added "Multicycles between clocks" to adjust for the time delay. I recompiled and got no timing warnings.  however, my output values keep on changing every time i refresh the instance in in-system memory editor.  I don't understand why this would happen. Your guidance and help will highly be appreciated.

[Altera_Forum]

Your post and mine were lost. 

 What I was implying is that your thoughts on clocking and multicycle are not right.  As to the solution, I think you need first to word(identify) the problem. It could be your output will not cycle exactly or your computation logic is buggy. I will put timing as last culprit if at all, check rtl simulation to exclude timing.

[Altera_Forum]

I ran a ModelSim-Altera simulation to confirm that my output (of my computation logic) is correct. 

 As you advised in another post, I added latency where ever necessary to try to minimize the path constraints.  The problem now is that after adding some latency, and by trying to avoid using the Multicycle-approach, I keep on getting slacks at some path or the other.  The weird part (at least to me) is that Quartus initially showed a slack in a path near the middle of the computational logic. Upon adding some latency/registers to correct for time delay near the middle path, Quartus then showed a slack near the starting of the design. And again upon correcting this slack using latency, a slack showed up some where in between the computation logic.  Why would Quartus not start showing the slack from the top and proceed towards the end?

[Altera_Forum]

I suggest full rtl simulation of all design including RAMs in order to verify that the write/read logic is doing its job.