Properly Constraining Inverted Clock with TimeQuest

[Altera_Forum]

I have only a limited understanding of TimeQuest and timing requirements in general, so please excuse my ignorance and lack of technical vocabulary on this subject. 

 I have an FPGA sitting between two HDMI daughter cards (RX and TX). My modules expect the clock to be posedge based, like so:  always @ (posedge pixel_clock) beautiful_color_data <= RX_RGB;  However, these new HDMI daughter cards are negedge based. My code is used in other designs, so I can't replace all the posedges. To fix the problem, I do this:  assign pixel_clock = !RX_PCLK; assign TX_PCLK = RX_PCLK;  That inverts the HDMI rx pixel clock, and my design works again. The clock is passed through unmodified, because the TX chip expects data to be negedge based (so giving it the inverted clock would obviously break things). However, TimeQuest throws up, and there are little timing mistakes in the output video (since timing isn't being constrained correctly).  So my question is, what is the correct way to constrain this design, and make TimeQuest happy? How do I define the set_input_delay and set_output_delay? Do I define it relative to pixel_clock, and tell TimeQuest that pixel_clock is a generated inverted clock based on RX_PCLK?  Please remember that I'm still new at timing, so go easy on me :)  Thank you!

[Altera_Forum]

1. Create a RX_PCLK base clock with  

create_clock -name RX_PCLKC -period ... [get_ports RX_PCLK]  2. Create a RX_PCLK_virt virtual clock with (create clock) create_clock -name RX_PCLKC_virt -period ...  3. Set your input delay constraints using RX_PCLK_virt and -clockfall set_input_delay -min ... -clock RX_PCLK_virt -clockfall [get_ports ... ] set_input_delay -max ... -clock RX_PCLK_virt -clockfall [get_ports .... ]  4. Create a TX_PCLK derived clock that is the same as TX_PCLK create_generated_clock -name TX_PCLK -source [get_ports RX_PCLK] [get_posts TX_PCLK]  5. Set your output delays relative to TX_PCLK using -clockfall set_output_delay -min ... -clock TX_PCLK -clockfall [get_ports ... ] set_output_delay -max ... -clock TX_PCLK -clockfall [get_ports .... ]  6. Create a generated inverted pixel_clock. create_generated_clock -name pixel_clock -source [get_ports RX_PCLK] -invert [get_nets pixel_clock]  However, I think Quartus will recognize this during synthesis and convert all the posedge logic fed by pixel_clock to negedge logic. If it does this, this create_generated_clock is problably unecessary and will problably fail as well.