Programmable Devices
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Keeping I/O pins to GND during power up

Altera_Forum
Honored Contributor II
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Hello everybody from southern Germany, 

 

I am using a CPLD in a design which drives 4 fullbridge mosfet 

drivers , and thus while the system is powering up I need to ensure 

that the I/O's which control the drivers remain at GND potentail the entire time while powering up.  

 

I have tried the ISP clamp option which definitely holds the  

I/O port low while programming, but the port still goes to VDD  

while ramping up power for about 250 uS which the fullbridge cannot 

tolerate. 

 

It seems like this may have more to do with the external circuitry to overcome 

the weak pullup, any ideas ? 

 

Thanks a bunch, 

Eric
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Altera_Forum
Honored Contributor II
194 Views

A strong pull-down?

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Altera_Forum
Honored Contributor II
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Use an isolator (optic or magnetic i.e. ADUM3440) between the FPGA and the mosfet driver. 

 

Only enable the isolator after the FPGA has powered up. 

The advantage of the iso is that it protects your FPGA.
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