A problem with DDR2 and PLL core in SOPC

[Altera_Forum]

In my SOPC design(Quartus II 10.1), both Avalon_altpll and DDR2 controller are used. And I can generate the nios core successfully. However, when I compile the whole design, the software always warning "Error: Node instance "altpll_component" instantiated with unknown parameter "clk0_divide_by"", and so on. This altpll is inside the DDR2 core. 

I don't know why. Can somebody help me?

[Altera_Forum]

Hi, 

 I have exactly the same problem! I want to instantiate a pll, but whether it be as a megafunction or within SoPC builder, it gives me that error. Did you find a way around it?  Cheers, Josef

[Altera_Forum]

That was quick... I found that it was some previous (corrupt?) instance of a pll that did not allow to implement a pll after that. I deleted all the previous pll files, and now it works