Custom memory interface

[Altera_Forum]

I need to create custom memory interface for fully-parallel memory (non-bidir) with separate data input bus, data output bus, write address and read address.  

 Where can I find literature or examples of how could such custom interface be created for SOPC?  So far I only found solutions with bidirectional interfaces with memory (altera.com/literature/lit-external-memory-interface.jsp).

[Altera_Forum]

I would start with reading the Avalon Memory Mapped (MM) slave information from the Avalon spec: http://www.altera.com/literature/manual/mnl_avalon_spec.pdf 

 If your memory is synchronous and supports multiple reads in flight pay extra attention to the pipeline read information in the spec so that you'll get the most throughput possible out of your memory.  Once you have the interface of your IP ready then you can feed the HDL through component editor which will bundle it as a component for use in SOPC Builder. http://www.altera.com/literature/ug/ug_sopc_builder.pdf