TimeQuest "Warning: Ignored filter ... could not be matched with a port"

[Altera_Forum]

I used the TimeQuest Timing wizard to generate an SDC file with setup and hold timing constraints. Here is a snippet from the file: 

  set_input_delay -clock "sinclk" -max 18ns set_input_delay -clock "sinclk" -min 2.000ns    I get the following errors regarding those lines:    Warning: Ignored filter at FpgaThird.sdc(40): da could not be matched with a port Warning: Ignored filter at FpgaThird.sdc(40): db could not be matched with a port Warning: Ignored set_input_delay at FpgaThird.sdc(40): Argument <targets> is an empty collection Info: set_input_delay -clock "sinclk" -max 18ns Warning: Ignored set_input_delay at FpgaThird.sdc(41): Argument <targets> is an empty collection Info: set_input_delay -clock "sinclk" -min 2.000ns    The file is generated by the Wizard, and it was aware of all the port names, so I'm lost as to why this error is arising.

[Altera_Forum]

Look in your .fit.rpt. Do these files exist? I've only seen this message when they truly don't work. Perhaps the wizard is looking at port names after elaboration, but they get synthesized out when running a full compile. Just a guess. Run TimeQuest on the back end and go to View -> Name Finder. You can direcly access the post-fit timing database from there.

[Altera_Forum]

A wild guess: your da and db ports are actually buses. If you want to apply constraint to the whole bus, try this: 

set_input_delay -clock "sinclk" -max 18ns db }] set_input_delay -clock "sinclk" -min 2.000ns db }]

[Altera_Forum]

--- Quote Start ---  A wild guess: your da and db ports are actually buses. If you want to apply constraint to the whole bus, try this: set_input_delay -clock "sinclk" -max 18ns db }] set_input_delay -clock "sinclk" -min 2.000ns db }]  --- Quote End ---    da and db are actually busses. Thanks for the  [*] suggestion. Previously I had manually enumerated each of the pins. Now I used  [*] but I still get an error:   Warning: Ignored set_input_delay at FpgaThird.sdc(40): Positional argument: object_list targets with value db }] contains no input ports Info: set_input_delay -clock "sinclk" -max 18ns db }] Warning: Ignored set_input_delay at FpgaThird.sdc(41): Positional argument: object_list targets with value db }] contains no input ports Info: set_input_delay -clock "sinclk" -min 2.000ns db }]

[Altera_Forum]

--- Quote Start ---  Look in your .fit.rpt. Do these files exist? I've only seen this message when they truly don't work. Perhaps the wizard is looking at port names after elaboration, but they get synthesized out when running a full compile. Just a guess. Run TimeQuest on the back end and go to View -> Name Finder. You can direcly access the post-fit timing database from there.  --- Quote End ---    As far as I know, these pins are not getting synthesized away, unless the compiler is doing so silently.  .fit.rpt does exist. What should I be looking for here? For the pins in question, I get the I/O assignment warning "Missing drive strength and slew rate". I'm going to try to add additional constraints to see if I can get rid of the warnings.  What do you mean by "Run TimeQuest on the back end"? I can run the TimeQuest analyzer, but the "View" menu does not contain a "Name Finder" option.  Thanks!

[Altera_Forum]

For deeper analysis, TimeQuest should be run as a stand-alone tools(the reports created during compilation are just high-level summaries of what domains are failing, but you need to run TQ separately to analyze specific paths). Just click on the stopwatch(not the one with the Play symbol) and the TQ GUI should come up.

[Altera_Forum]

That's the GUI I had been using. I still don't see View->Name Finder 

 I'm using Quartus 10.1 Build 197.

[Altera_Forum]

It's got to be in there somewhere. Can you provide a screenshot? 

If you want to do it by hand, type the following into the console at the bottom:  set col [get_ports {da[*]}] query_collection -report $col  If that works, then the ports exist, then maybe they're not inputs.

[Altera_Forum]

I had already compiled the design, but I didn't realize that the Timing Netlist hadn't been created yet when I re-opened TimeQuest. The Name Finder option appeared after that. Thanks for listing the command line interface commands. 

 It looks like all the port names are valid. I've attached some screen shots that show them listed.

[Altera_Forum]

Are you sure they're inputs? What happens if you run: 

report_path -from [get_ports {da[*]}] -panel_name "rp input test" report_path -to [get_ports {da[*]}] -panel_name "rp output test"  (I think that's correct)

[Altera_Forum]

Hm I still have this problem. 

 Right now I'd like to constrain the timing on an input.    report_path -to }] -panel_name "rp output test" Info: Report Path: No paths were foundSo it looks like TimeQuest recognizes the port name.  When I compile the design, though:  Warning: Ignored filter at smr.sdc(40): adc_d_a could not be matched with a port Warning: Ignored filter at smr.sdc(40): adc_d_b could not be matched with a port Warning: Ignored set_input_delay at smr.sdc(40): Argument <targets> is an empty collection Info: set_input_delay -clock "data_conv_clk_b" -max 4.200ns adc_d_b }] Warning: Ignored set_input_delay at smr.sdc(41): Argument <targets> is an empty collection Info: set_input_delay -clock "data_conv_clk_b" -min 2.900ns adc_d_b }]

[Altera_Forum]

You switched your a and your d, i.e. adc_a_d worked in report_path while adc_d_a does not work.

[Altera_Forum]

D'oh! thanks!