integer data type

Altera_Forum · ‎04-02-2011

hello everyone,

I need help here.Below is my vhdl code:

LIBRARY ieee;

USE ieee.ALL;

ENTITY haar IS

PORT (

clock : IN bit;

clk : IN bit;

-- Inputs

in1 : IN integer RANGE -127 TO 127;

in2 : IN integer RANGE -127 TO 127;

in3 : IN integer RANGE -127 TO 127;

in4 : IN integer RANGE -127 TO 127;

in5 : IN integer RANGE -127 TO 127;

in6 : IN integer RANGE -127 TO 127;

in7 : IN integer RANGE -127 TO 127;

in8 : IN integer RANGE -127 TO 127;

--Outputs

out1 : OUT integer RANGE -127 TO 127;

out2 : OUT integer RANGE -127 TO 127;

out3 : OUT integer RANGE -127 TO 127;

out4 : OUT integer RANGE -127 TO 127;

out5 : OUT integer RANGE -127 TO 127;

out6 : OUT integer RANGE -127 TO 127;

out7 : OUT integer RANGE -127 TO 127;

out8 : OUT integer RANGE -127 TO 127

);

END haar;

ARCHITECTURE haar OF haar IS

begin

PROCESS(clk)

BEGIN

IF clk'EVENT AND clk = '1' THEN

output <= input;

END IF;

END PROCESS;

END haar;

My question is why when i create the waveform file for the code, the pins is not same as the expected pins? I get the input pins like below:

in1[0]

in1[1]

in1[2]....in1[7]

But, that is not i want.Suppose the input is like:

in1, in2, in3,....in8.

Can anyone help me solve this problem?.

Altera_Forum · ‎04-02-2011

Each of your ports translates to 8 bits in Hardware terms.

I wonder what

output <= input;

means as these names are not declared or did you just say it for short...

Altera_Forum · ‎04-02-2011

the code above is for short..Actually i obtain the based on the pipelined architecture that i has been designed.It consist of 3 stage and include 3 basic component.I try to troubleshoot the coding by simulate stage by stage,but the problem occurs is same..why?

Thanks for reply.

Altera_Forum · ‎04-02-2011

You don't have any problem thus far. You are asking in1 to be range -127 ~ 127 i.e. 8 bits. so is in2 and so on...

Altera_Forum · ‎04-02-2011

Sorry, i don't understand what u said..It is mean that the input pins i get;

in1[0], in1[1], in1[2]....in1[7] is correct?

Altera_Forum · ‎04-02-2011

--- Quote Start ---

I get the input pins like below:

in1[0]

in1[1]

in1[2]....in1[7][/QUOte]

where do you get like this?

Altera_Forum · ‎04-02-2011

I get the pins at the vector waveform file..in the node finder.

Thanks for reply.

Altera_Forum · ‎04-02-2011

--- Quote Start ---

I get the pins at the vector waveform file..in the node finder.

--- Quote End ---

I see, but I don't know why. You can rearrange them by using the grouping feature.

Altera_Forum · ‎04-02-2011

Thanks FvM..can i ask one question, what actually the function of buffer in vhdl code?