Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16612 Discussions

Has anyone used tcl created verification task for virtual JTAG

Altera_Forum
Honored Contributor II
‎04-02-2011 04:34 AM
1,052 Views

Dear All. 

 

Are there anyone who has used virtual JTAG? 

 

I want to write an stimuls like my testbench does, but don't know how to emulate clock edge event in tcl. 

 

I need to use tcl implement following function. 

 

@ (posedge clk) 

 

xxxx; 

 

Has any suggestion? 

 

Thanks!
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎04-04-2011 04:12 PM
333 Views

Yes, I have used Tcl to verified a design that included a virtual JTAG interface that accessed embedded TDRs. To run the actual hardware, I wrote Tcl scripts and used Intellitech's free software tool, NEBULA. It has full Tcl support and even has an integrated Tcl single stepper. You can download it at the Intellitech website. You'll need a Xilinx Platform Cable USB pod too, but you may already have one. If not, they are affordable. Let me know how you make out. 

 

p.s. Sorry that I can't post links to the free download to this forum yet, but you can search the internet for "free jtag intellitech" and the link should show up. 

 

-Craig
0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.