DDR2 interface between FPGA and MCU

[Altera_Forum]

Hello, 

 Could you please help me with some questions.   I use CycloneIII(EP3C16F484).  I am designing a DDR2 interface between FPGA and MCU.  This means FPGA operates like DDR2 SDRAM.  I'm not sure whether ALTMEMPHY for DDR2 is suitable for my design because of signal directions.    Q1) Is it possible to use ALTMEMPHY for DDR2 in my design ?  Q2) If Q1 is No, is it possible to customize and meet timing for DDR2 in my FPGA ?  Q3) If MCU does not have SSTL-1.8 Class-I termination scheme, do I have to  implement "parallel termination on board" and   "series termination on chip (OCT of FPGA)" ?   Q4) Is it important the location (Rx side or Tx side) of SSTL-1.8 series termination   resistor?   Thank you

[Altera_Forum]

An interface between an MCU and a FPGA can use DDR signalling with several votalge standards possible. DDR2 is specific for Synchronous SDRAM and has the SSTL-1.8 requirement. 

A1) No. It is probably totally inappropriate. A2) Yes. A3) You should be able to use series termination, especially if you have unidirectional interface(s). You can also do series termination for bidirectional interfaces, but you have to account for the remote series resistor in the rise time/delay of the signals. If you implement the series termination resistor in the FPGA for a bidirectional pin, this resistor will only be seen/active in the output path. A discrete termination on the MCU side will be add a delay in both directions. A4) A 'series termination resistor' is always on the TX-side.   Q: what MCU do you want to interface?

[Altera_Forum]

Thank you josyb 

 I will use DDR2 interface of "S5PC110".

[Altera_Forum]

I took a quick look at the MCU. (a deeper look requires a NDA ...) IMO the only DDR interface is the one to attach the main memory for the SoC. If you want to connect to this interface you will very likely have to use the SSTL-1.8 voltage drive, but furthermore the FPGA will have to act as a DDR memory device. Apart from your reasons to do so, the required interfacing will not be that difficult as the JEDEC DDR2 specification puts the difficulties at the controller side which in your set-up is the SoC.