Confusion about Source-Synchronous constraints

[Altera_Forum]

Hi, everyone: 

 I use FPGA to capture the output data of ADC. The ADC output timing is as follows: https://www.alteraforum.com/forum/attachment.php?attachmentid=3894   In Altera's "AN 433 Constraining and Analyzing Source-Synchronous Interfaces", it says source-synchronous interfaces have two branches on Clock and Data Relationship -- edge-aligned and center-aligned, which is shown as follows: https://www.alteraforum.com/forum/attachment.php?attachmentid=3895  https://www.alteraforum.com/forum/attachment.php?attachmentid=3896   So the ADC output timing is center-aligned. It seems that I can directly use COUT to capture the data DAB. am i right here?  Then I turned to http://www.altera.com/support/examples/timequest/exm-tq-ca_ss_in.html for helps on the constraints. But the Sample SDC File on the page contains the shifted clock constraint. This tells FPGA to shift COUT about 90 degree. am i right here?  If all my personal hypothesis is right, FPGA first shift COUT then use the shifted clock to latch DAB, which may causes hold timing issue. Can anyone help me with this idea? I am really confused about it and thank you in advance!  ===== PS: On page 5 of "Best Practices for the Quartus II TimeQuest Timing Analyzer", there's a figure: https://www.alteraforum.com/forum/attachment.php?attachmentid=3898  The corresponding constraint example:   --- Quote Start ---  #create base clock for the design create_clock -period 10 -name clk_in [get_ports clk_in] # create the virtual clock for the external register create_clock -period 20 -name virt_clk -waveform {0 10} # set the output delay referencing the virtual clock set_output_delay -clock virt_clk -max 1.5 [get_ports data_out]  --- Quote End ---    Since data_out port is within external device, I think the blackened line is to constrain the output timing of external device. Is it an amazing function or some small neglect?

[Altera_Forum]

For ADC you need to set input delay.  

The virtual clock is used for input delays, not output delay, I don't know from where you got your example.  If your ADC data is centre aligned and stays so at FPGA then you don't need to rotate a clock that is already rotated for you.  You need to set input delay at the fpga according to tCO of ADC which equals half UI if ADC is centre aligned.  You can use virtual clock if you want to tell fpga the about board delays but is not necessary. What matters is that fpga knows relation of ADC data to clock at fpga pins.

[Altera_Forum]

Thank you for your quick reply, sir. 

However, I have something to be further clarified:    --- Quote Start ---  I don't know from where you got your example.  --- Quote End ---   It's from "Quartus II 10.1 Handbook, Vol. 3, Chap 7, Page 5, Example 7–6" and I am confused about the set_output_delay, too. So I want to make sure what's going on with the situation.    --- Quote Start ---  You need to set input delay at the fpga according to tCO of ADC which equals half UI if ADC is centre aligned.  --- Quote End ---   I just began to use altera's device and develop tools. Could you please show me the meaning of "UI"? Thanks.    --- Quote Start ---  What matters is that fpga knows relation of ADC data to clock at fpga pins.  --- Quote End ---   This really helps me. Thank you very much.

[Altera_Forum]

Hi, 

 UI is the lazy format for Unit Interval. i.e. clock period(if interface is single data rate) or (half clock period if interface is DDR).  Don't worry about virtual clock or set output issue. Just enter set input delay and that should be enough. If you don't get timing right then you can look for other options.

[Altera_Forum]

I understand this issue better. Thank you very much for your help.