SYSTEM_INFO to vhdl parameter

[Altera_Forum]

Hi, 

 I would like to automatically pass the clock frequency to the generated component. For this I added a line in the _hw.tcl file to use the SYSTEM_INFO property.  Unfortunately, the component is always generated with the default value of the parameter, not with the value of the clock it is connected to (ie. 50MHz).  FILE _hw.tcl ... add_parameter SYSFREQ NATURAL 1 set_parameter_property SYSFREQ DEFAULT_VALUE 1 set_parameter_property SYSFREQ DISPLAY_NAME SYSFREQ set_parameter_property SYSFREQ UNITS None set_parameter_property SYSFREQ DISPLAY_HINT "" set_parameter_property SYSFREQ AFFECTS_GENERATION false set_parameter_property SYSFREQ HDL_PARAMETER true set_parameter_property sysfreq system_info {clock_rate clk} ...  FILE .vhd ... entity my_component is  generic (  sysfreq : natural := 1  );  port (  -- global signals  signal clk : in std_logic;  signal reset : in std_logic; ...  FILE generated component ...  my_component_0 : component my_component  generic map (  sysfreq => 1  ) ...  Is my approach correct ? If not, how should the value be passed to the component ?  Thanks for your help, P9

[Altera_Forum]

found my mistake : the argument to SYSTEM_INFO CLOCK_RATE must be the interface name (mostly clock_reset), not the clock signal's name. 

 FILE _hw.tcl ... add_parameter SYSFREQ NATURAL 1 set_parameter_property SYSFREQ SYSTEM_INFO {CLOCK_RATE clock_reset} set_parameter_property SYSFREQ AFFECTS_GENERATION false set_parameter_property SYSFREQ HDL_PARAMETER true set_parameter_property SYSFREQ VISIBLE false ...