Hi,
I used Verilog for Asic designs a long time ago (more than 10 years). For the last several years I have been doing Altera designs with AHDL.
I know that Verilog has gone through changes over the years and now "System Verilog" is in what is current.
I also know that only a subset of the language can by synthesized by FPGA software.
So, my question is: knowing that my use if for FPGA design, can anyone recommend a good text reference or in depth tutorial source for re-learning Verilog with respect to Altera design software?
Thank You
Tom
