Cyclone IV M9K packed-mode RAM

[Altera_Forum]

Hello, 

 I use the Megafunction of Quartus II to generate a single-port RAM. I implemented that IP at many places in my RTL design. After doing compilation, I expect that the resourse ultilization is one M9K for every two single-port RAM (I am using cyclone IV device), but the Quartus II reports that a M9K is used for a single-port RAM.  A single-port RAM is generated with single-clock mode and size is under 4K bit (depth is 64-word and width is 8-bit data).  Please advice me how to use packed-mode feature for this device. Because my RTL design has many RAM with size under 1K-bit, and I want to utilize the memory block (M9K) effectively.  Many thank for your help!

[Altera_Forum]

I believe RAM packing occurs in the fitter, i.e. if it needs to the fitter can merge RAM cells into an M9K. If it doesn't need to though, it won't, as this provides more flexibility and better timing. Are you getting a no-fit? If not, you need to add more memories to see if it starts merging them. (Perhaps but a block into a LogicLock region that's small enough to require RAM merging)