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Source Synchronous Input Edge Aligned DDR

Altera_Forum
Honored Contributor II
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Hi all, I'm trying to figure out how to solve correctly the following problem. 

 

I've a source synchronous interface edge synchronous between an AD and mu FPGA (Altera Stratix IV 180). 

A clock distributor send the same CLK to both FPGA and to DDS, and DDS output clock and data signal to fpga. 

 

In attachment you find a diagram of connections and the chosen AD is Intersil ISLA112P50 (you can find the data sheet here: http://www.intersil.com/data/fn/fn7604.pdf and our timing information are at page 8-9: I use LVDS output grey coded) 

 

CLK supplied as clk in to DDS is 2.53 ns (448 MHz), DDS outputs to FPGA a clock that is 224MHz and data together with this clock are edge aligned and DDR. 

 

On Altera AN 433 it's tell to use a PLL in source synchronous mode in order to shift the internal FPGA clock in the middle of the data, but I ran out PLL (design is quite complex) and moreover CLK out from DDS can be stopped (each time there is a calibration, but in calibration I'm not interested in DATA so I could use the pll maybe, but I've to check the design in order to see if pin chosen for AD input shall be driven to the free PLL). 

 

I've discarded to use the clk referenced to FPGA by clock distributor because the phase relationship between it and the AD clk out is very undefined (I mean that I've a min of 1.8ns and a max of 3.6ns so regarding my 2.23 ns) so seems that I've only 400ps to use.. maybe I shall think about theese 400ps... 

 

Told that I'm struggling thinking of an idea to make the FPGA take data correctly. 

Ideas I'm considering 

1- My actual idea is that I use DDS data and clock out to fpga and I try to tell FPGA that it have to sample data 1 ns after the clock: if I do not use a global lines I could accomplish this task but I think that the timing analisys will be a nightmare... 

2- Do you remember those 400ps? Yep I'm thinking to use them. 

We are saying that in a 2.43ns of clock period we've an uncertainty of 1.8ns, moreover from clk to data we've an uncertainty of 0.5 ns (+/- 250 ps) so in total we've 2.3ns of uncertainty against 2.43ns of clk period... 

Mumble.. very difficult.. 

3- I shall try to see if I can use the PLL freeing 1 of them.
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Altera_Forum
Honored Contributor II
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Being that this is a source synchronous interface, you should use the clock from the A/D to capture the data in the FPGA. You can probably get away with not using a PLL to shift your clock into the center of the data valid window at this frequency. If the inputs are constrained properly, then the programmable delays on the I/Os will take care of shifting the data relative to the clock to meet your setup and hold requirements giving you positive slack.

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