Problem with multiple DDR2 controllers in Arria GX.

[Altera_Forum]

Hello, 

   I have a question related to an Arria GX EP1AGX50DF780C6 project. There are two instances of the "DDR and DDR2 SDRAM High-Performance Controller MegaCore v10.1", each connected to a Micron MT47H16M16 DDR2 chip. These memories are 16 bit wide and are clocked at 200MHz. The FPGA internal datapath runs at 100MHz and is 64 bit wide.     The controllers are named CTRL1 and CTRL2 and are istantiated in a SOPC architecture with a NIOS and several peripherals.     The CTRL1 is a complete controller, with its dedicated PLL and DLL, while CTRL2 is configured to share static clocks with CTRL1 (option "Multiple Controller Clock Sharing/Use clocks from another controller"). The CTRL2 is also configured to "Istantiate DLL externally". Without the second option the FPGA would not fit since both DDR2 are on the same (bottom) side of the device.     After compilation, timing analisys reports good fast and slow model timings for CTRL1, while CTRL2 has problems with slow model timings:     Info: setup hold  Info: Address Command (Slow Model) | 2.183 1.195  Info: DQS vs CK (Slow Model) | 1.207 1.250  Info: Half Rate Address/Command (Slow Model) | 7.195 1.163  Info: Mimic (Slow Model) | 0.788   Info: Phy (Slow Model) | 0.156 0.490  Warning: Phy Reset (Slow Model) | -0.070 1.048  Info: Read Capture (Slow Model) | 0.156 0.675  Warning: Read Postamble (Slow Model) | -1.891 4.785  Info: Read Postamble Enable/Disable (Slow Model) | 0.284 1.716  Info: Read Resync (Slow Model) | 1.115 1.115  Info: Write (Slow Model) | 0.341 0.672     By using the Chip Planner I have seen the two CTRL1 postamble enable registers are correctly placed close to the DQS pins that they are driving, while the two CTRL2 postamble enable registers (called postamble_en_pos_2x[0] and postamble_en_pos_2x[1]), are placed in the middle of the FPGA.     If I constraint the fitter to place CTRL2 postamble enable registers close to the DQS pins with a set_location_assignment like the following ("..." replaces superfluous text), the FPGA would not fit.     set_location_assignment LAB_X23_Y1 -to "...|postamble_en_pos_2x[0]"  set_location_assignment LAB_X25_Y1 -to "...|postamble_en_pos_2x[1]"     The error messages are in the attached file.     Nothing changes if I constraint location of CTRL2 PLL. Is there a way to constraint the CTRL2 postamble enable registers location and fit the FPGA?     I have tried the following Quartus II releases:     Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition  Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition  Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version     Best Regards,  Sergio