Initialization of AD7194 using SPI and Cyclone 2

[Altera_Forum]

Hi All, 

 I am new to verilog.   I am trying to initialize ADC AD7194. For this I am using SPI protocol and I am trying to obtain the wave forms as shown in the attached image. In the image, CS is the chip select, Din is the input to the ADC, SCLK is the SPI clock and Dout is the ouput from ADC.  I am able to generate the SCLK and send data at every negative edge of the clock. But for the correct initialization, we have to provide a delay of 250ms after each word is sent to the ADC. And also. as it can be seen from the waveforms, SCLK does not toggle continuously but it remains high during this delay.  I do not know how to give this delay and keep SCLK high for 250ms. Please give me ideas as how to achieve this. Any kind of code will help.   I know# <delay> works only in simulations and not in hardware  I am using Quartus II and Cyclone 2 DE1 board.   Any kind of help is greatly appreciated.  Thanks in advance

[Altera_Forum]

The delay work should be realized by flip-flop or ram

[Altera_Forum]

Thanks for the reply. Can you please explain in more detail and give some example

[Altera_Forum]

you can add some reversers ,but need to caculate the time... 

 personal idea, some protocol is hard to realize in HDL. Some ip for control AD or SDRAM is complex. that is why many people use NIOS. It`s a good interface.   abort dealy .... just now I remember the DSP-builder Z^-1 used by filter, the module is in the storge in simulink. just now my talk seems wrong.

[Altera_Forum]

you may find some opencore for control AD ip. certainly official ip is strick.