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pausing target processor: not responding

Altera_Forum
Honored Contributor II
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hi all, 

i hav build a system in sopc builder using nios ii cpu, jtag_uart, esps_flash_controller, ddr_high_performance_memory_controller, tse_mac, sgdma_rx, sgdma_tx, flash_tristate_bridge, ext_flash, and an onchip_memory. i managed to compile it successfully. 

 

i downloaded the hardware image into fpga and now am trying to run a simple hello_word program on nios ii processor. but it is not happening. 

the following message is being displayed in the console. . . 

 

using cable "USB-blaster [USB-0]", device 1, instance 0x00 

pausing target processor: not responding 

presetting and trying again : FAILED 

leaving target processor paused 

 

if anybody knows why this is happening pls help me. . .  

 

thank you. . .
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Altera_Forum
Honored Contributor II
1,671 Views

Search the forum. This is a faq. 

Common problems: 

- are you using unlicensed cores in OpenCore mode? Then you should not close the USB-Blaster message upon fpga configuration 

- check if your Quartus design meets all timings
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Altera_Forum
Honored Contributor II
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Or it is not coming out of reset. Make sure you have all clocks present and your reset sequence is correct.

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Altera_Forum
Honored Contributor II
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thanks for your reply. . . 

 

to cris, 

 

am using quartus ii 8.1v which i downloaded from the net and there it is mentioned that no licence required. 

 

before i used niosii_ethernet_standard design example there i managed to run hellow_word pgm on nios ii processor, but the problem is with the system which i have built. 

 

am not closing open core plus window, in my case am using an ip which will reset after an evaluation time of 4 hours so the time remaining is 4 hours. 

is this the reason which is causing that problem. . . 

 

 

thank you. . .
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Altera_Forum
Honored Contributor II
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Are you sure about timings? 

Which device are you using and what are clock frequencies for Nios, ddr and tse? 

 

Also check if all signal are assigned to the correct pins. Maybe you missed some.
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Altera_Forum
Honored Contributor II
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hi, 

 

these are the timing related warnings i am getting 

 

warning:  

1.at least one of the filters had some problems and could not be matched. 

2.the following clock transfers have no clock uncertainity assignment 

3.critical warning: timing requirements not met. 

4.critical warning: found minimum pulse width or period violations. see report minimum width for details. 

 

i dont know how to overcome these. 

 

sorry my questions may seem silly, but i cant help this is my first experiance with altera environment. 

 

am using cyclone iii dev board ( ep3c25f324c6). 

 

my mentor said it is some interrupt related error. is that the one causing problem...? 

 

thank you.
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Altera_Forum
Honored Contributor II
1,671 Views

hi, 

 

i haven't added system id pheripheral is it anyway related to that.
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Altera_Forum
Honored Contributor II
1,671 Views

 

--- Quote Start ---  

 

i haven't added system id pheripheral is it anyway related to that. 

--- Quote End ---  

 

 

Is this a question or your conclusion? 

The behavior you reported is not likely due to this, unless you have loaded a wrong fpga configuration and disabled sys id check. 

The critical warnings about timing are probably the real issue. 

You can try to raise the Quartus compilation effort to overcome the problem or activate timing driven synthesis, if you haven't done it already. 

What clock frequency are you using? Maybe it's too high for your EP3C25 device: with all the components you listed I'd suggest to keep it below 100MHz.
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Altera_Forum
Honored Contributor II
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hi, 

actually it was a question.. 

 

except memory clock frequency (125 MHz) all are below 100MHz. 

 

what do you mean by raising the quartus ii compilation effort. . ???  

and i have activated time quest analyzer during synthesis. how to activate timing driven synthesis. . .?? 

 

thank u. . .
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Altera_Forum
Honored Contributor II
1,671 Views

hi cris, 

 

i made some changes and recompiled my project again, now there are no warninigs related to timings. but still the problem exists. 

 

i am not getting what should be done. if anybody knows how to overcome this problem pls help me. . . 

 

thank you.
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Altera_Forum
Honored Contributor II
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One way to start would be to put in signaltap and look at all of your clock networks and reset trees. If one of your clocks doesn't pop up or one of your resets doesn't release, your whole system may be stuck in reset. From personal experience this is what causes my systems to not respond. 

 

It is also good practice to put in a sys id block. In your current case it won't matter because it never gets to the point where it checks it, but once you do get your problems figured out it will help.
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Altera_Forum
Honored Contributor II
1,671 Views

hi, 

 

thank you cris and kbs972 for ur replies. 

 

i rebuilt my system, i removed ext_flash component and instead of ext_flash i set on_chip memory as reset vector of nios ii.  

 

now pausing target processor problem doesn't exist. 

 

but nothing is getting printed in the console 

 

am getting the following messeges: 

 

nios2_terminal: connected to H/W target using UART on cable 

nios2_terminal: "USB-Blaster[ USB-0]",device 1,instance 0 

nios2_terminal: (use the IDE stop button and Ctrl-C to terminate) 

 

but hello from nios ii is not getting printed. 

 

pls help me. 

 

thank you.
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Altera_Forum
Honored Contributor II
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Check if you selected UART as stdout device. 

Also make sure your target is running; if you have a spare PIO or a LED you can toggle it to monitor program execution.
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Altera_Forum
Honored Contributor II
1,671 Views

hi, 

 

yeah i have set stdout as jtag_uart  

 

and for toggling LED where i should write code, in nios or in quartus. . .??
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Altera_Forum
Honored Contributor II
1,671 Views

 

--- Quote Start ---  

 

and for toggling LED where i should write code, in nios or in quartus. . .?? 

--- Quote End ---  

 

 

In Nios program. 

Say you have a spare PIO port named led_out, possibly connected to LEDs.  

Then you can toggle the first pin by calling periodically this function: 

 

# include "altera_avalon_pio_regs.h" void PIO_pin_toggle(void) { alt_u8 pio; pio = IORD_ALTERA_AVALON_PIO_DATA(LED_OUT_BASE); IOWR_ALTERA_AVALON_PIO_DATA(LED_OUT_BASE, pio ^ 1); } 

 

This way you can easily monitor if your Nios program starts, keep running or hangs at some time. 

 

Regards 

Cris
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Altera_Forum
Honored Contributor II
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hi, 

 

one more thing, i hav a software demo program which i should run on nios ii and i created a new project and tried to compile it. 

 

it is a demo program given by vendors. 

 

while building project am getting following error 

 

make -s all includes  

Creating generated_app.mk... 

Creating system.h... 

Apr 28, 2011 1:54:06 PM - (SEVERE) generate: java.lang.IllegalStateException: java.lang.IllegalStateException: java.lang.NumberFormatException: empty String 

make[1]: *** [system_description/../obj/system.h-t] Error 1 

make: *** [system_project] Error 2 

Build completed in 94.297 seconds 

 

does anyone have idea why this is occuring. . .??? 

pls help me. . . 

 

thank you. . .
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Altera_Forum
Honored Contributor II
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Maybe the demo project was created with a different version of the dev tools. 

Did you create a new project and then added demo source files, or did you import an existing project? 

Also check if your Nios projects points to the correct sopc system and possibly regenerate it.
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Altera_Forum
Honored Contributor II
1,671 Views

 

--- Quote Start ---  

In Nios program. 

Say you have a spare PIO port named led_out, possibly connected to LEDs.  

Then you can toggle the first pin by calling periodically this function: 

 

# include "altera_avalon_pio_regs.h" void PIO_pin_toggle(void) { alt_u8 pio; pio = IORD_ALTERA_AVALON_PIO_DATA(LED_OUT_BASE); IOWR_ALTERA_AVALON_PIO_DATA(LED_OUT_BASE, pio ^ 1); } 

 

This way you can easily monitor if your Nios program starts, keep running or hangs at some time. 

 

Regards 

Cris 

--- Quote End ---  

 

 

thank you cris, 

i ll try this and let you know the result.
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Altera_Forum
Honored Contributor II
1,671 Views

 

--- Quote Start ---  

Maybe the demo project was created with a different version of the dev tools. 

Did you create a new project and then added demo source files, or did you import an existing project? 

Also check if your Nios projects points to the correct sopc system and possibly regenerate it. 

--- Quote End ---  

 

 

no cris those demo files are created with same version of dev tools. . . when i installed those software files they appeared in the nios ii IDE similar to other templet programs (e.g.hello world) 

 

i selected that templet and selected build project thats all. . .
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CGiur
Beginner
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I know this is some 8 years late but just ran into it. In my case I hooked up a memory mapped slave (other than the internal bram) to the instruction master rather than data master of the nios2 in Qsys.

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