JTAG to Avalon master bridge usage

[Altera_Forum]

Hi, 

 The main issue i want to ask is whether the jtag to avalon master bridge IP core can be used to communicate data between PC and the FPGA, even if the board does not have JTAG connector. My board is terasic de4, and it has only a USB blaster, which can be configured in JTAG mode. I need to write some registers in the FPGA through System Console using master_write_32 command. I made a design with jtag to avalon master bridge as master to write to some Memory Mapped slaves. Can this be done through the USB blaster in JTAG mode or does the board need additional JTAG connecter for this functionality.  Thanks in advance

[Altera_Forum]

you can use a USB Blaster

[Altera_Forum]

Hi, 

 Thanks a lot for the reply. I tried communicating through system console, but was getting some errors.  set jtag_master [lindex [get_service_paths master] 0] open_service master $jtag_master  The above two commands worked properly. But when i tried the command master_write_32 $jtag_master 0x400 0x00000000, i am seeing the following error.  error: java.lang.RuntimeException: This transaction did not complete in 60 seconds. System Console is giving up. while executing "master_write_32 $jtag_master 0x400 0x00000000"  What could possibly be a reason for this error. is_service_open command returns 1.  Thanks in advance

[Altera_Forum]

Have you got any other jtag services that can be seen as master 0? (It happened to me that the 0 position in the list was occupied by Nios2; it only happened once and I do not know why). 

Are you sure the slave you are addressing is compliant to avalon specifications? If it is a custom one, try putting a SignalTapII instance and watch if the handshake on the avalon slave interface proceed as you expect.

[Altera_Forum]

The first thing I would check if you're getting this kind of error is that your clocks are running and resets are releasing properly. If the first access fails that is normally the cause.  

 You can use the jtag_debug commands to do this, or if that doesn't help then I'd go for SignalTap next.

[Altera_Forum]

Hi, 

 Thanks a lot guys. The issue was with my clock. I found the clock which i had assigned not toggling in the Signal Tap. I changed the assignment and it is working fine now.  Regards Hari

[Altera_Forum]

Hello Everyone, 

 I need some help with using System Console. I have created a Qsys system that consists of a JTAG to Avalon Master Bridge (Master) and an Avalon Memory Mapped Slave. The slave is created using a .vhd file which has the following ports:   csi_clockreset_clk : in std_logic; csi_clockreset_reset_n : in std_logic; avs_qsys_read : in std_logic; avs_qsys_readdata : out std_logic_vector(15 downto 0); avs_qsys_write : in std_logic; avs_qsys_writedata : in std_logic_vector(15 downto 0); avs_qsys_address : in std_logic_vector(15 downto 0); coe_writedata_ext : out std_logic_vector(15 downto 0); coe_write_ext : out std_logic; coe_read_ext : out std_logic; coe_address_ext : out std_logic_vector(15 downto 0); coe_reset_ext : out std_logic; coe_clk_ext : out std_logic; coe_readdata_ext : in std_logic_vector(15 downto 0)   And, I perform the following assignments:   coe_writedata_ext <= avs_qsys_writedata; coe_write_ext <= avs_qsys_write; coe_read_ext <= avs_qsys_read; coe_address_ext <= avs_qsys_address; coe_reset_ext <= csi_clockreset_reset_n; coe_clk_ext <= csi_clockreset_clk; avs_qsys_readdata <= coe_readdata_ext;   The address map for the Qsys is 0x00000000 to 0x0001FFFF. Now, I used this Qsys system and an external RAM (megawizard function) to perform reads and writes to the memory. I am using System Console, in Qsys, to run a TCL script to perform reads and writes using the following commands: master_write_16 and master_read_16   I have also added a signaltap file to the project to monitor changes in the signal values. Now, in the System Console window in order to read and write to address 0x0000, I used the following commands: 1. master_write_16 $jtag_master 0x0000 0x1 2. master_read_16 $jtag_master 0x0000 1   After each command I check the values shown by signaltap. For all the address entries, the data written and read for the memory is consistent. But, the address shown by signal tap (coe_address_ext) is not the same as the address I accessed using the TCL command.   I do not understand as to why is the address value captured by signaltap different then what I am entering using tcl command. Is there some kind of address mapping?    I will appreciate if someone can help me with the issue. Thanks.

[Altera_Forum]

The qsys fabric alters the address between master and slave in two (sometimes three) ways: 

* It subtracts the base address of the slave from the address provided by the master - so if you slave is at base address 0x4000 then byte address 0x4010 on the master will be seen as byte address 0x10 on the slave * If the master or slave is marked as being word addressed (one of the interface properties controls this) then the fabric will shift the address to convert it to/from a byte address * If the slave is marked as natively addressed then the fabric does all sorts of weird stuff. Native addressing is deprecated and should not be used.

[Altera_Forum]

Thank you for replying, 

 I do not want the address to get messed up internally. How am I supposed to make sure that I am not using native addressing? Am I supposed to use byteenable? By default byteenable for master is 4 bits and for my design the byteenable for conduit slave is 2 bits. Do I have to set a value to the byteenable or the system will understand that I am setting the master byteenable to "0011"? I tried doing it, but this gives the same result.   Or if I make my readdata and writedata of slave to be 32 bits then I need to set the byteenable to 0011. But byteenable is an input signal within qsys system. Where can I set a value for byteenable?

[Altera_Forum]

It would help if you said how your address appears to be getting messed up. 

 I'm guessing that the address provided by the master it is shifted right by one bit when it arrives at the slave (it's a 16 bit slave on a 32 bit master). The byteenables will be 11 if the master did a 16 bit access (or larger), 01 or 10 if the master did a byte access.  For a 16 bit slave you can shift the word address left by one bit and use ~byteenable[0] at your least significant byte address bit. It's a little more complex for 32 bit slaves.  I think there is a way to ask for byte addresses but I can't find it right now.

[Altera_Forum]

--- Quote Start ---  It would help if you said how your address appears to be getting messed up.   I'm guessing that the address provided by the master it is shifted right by one bit when it arrives at the slave (it's a 16 bit slave on a 32 bit master). The byteenables will be 11 if the master did a 16 bit access (or larger), 01 or 10 if the master did a byte access.   For a 16 bit slave you can shift the word address left by one bit and use ~byteenable[0] at your least significant byte address bit. It's a little more complex for 32 bit slaves.   I think there is a way to ask for byte addresses but I can't find it right now.  --- Quote End ---     Thank you so much. This is what is happening internally with the addresses. For the master_read_16 commands-- Master address = 0x00 ……………………………. Slave address = 0x00 Master address = 0x04 ……………………………. Slave address = 0x02 Master address = 0x08 ……………………………. Slave address = 0x04 Master address = 0x0C ……………………………. Slave address = 0x06   For the master_write_16 commands-- Master address = 0x00 ……………………………. Slave address = 0x02 Master address = 0x04 ……………………………. Slave address = 0x04 Master address = 0x08 ……………………………. Slave address = 0x06 Master address = 0x0C ……………………………. Slave address = 0x08 I get it that the address provided by the master it is shifted right by one bit when it arrives at the slave. This is indeed happening when I perform master_read_16. But when for master_write_16 this is not true. Why is the internal address mapping different for reads and writes? Also Byteeable is always 00 while write operation. Is that right?  Also it seems like if I only create a 2 bit byteenable for the slave and do not set master byteenable to 0011 ( I do not know how to set it), this is exactly same as having no byteenable in the slave. Probably that make it native addressing and not dynamic.

[Altera_Forum]

I think you said you were building the fabric using QSYS? I'm pretty sure that QSYS does not support native addressing, it treats native slaves as if they were 32 bit dynamic slaves. This looks the same to 32 bit masters (Nios II, JTAG Avalon Master etc). If you had managed to enable native addressing then this would not cause the issue with reads and writes behaving differently. 

 If the address mapping is different for writes and reads then this could be a bug. Can you signaltap the signals on the JTAG Avalon master as well as on your slave please - the master address should match the address passed in from SystemConsole for both writes and reads.  The byteenable behaviour you'll get depends on how you wrote your hw.tcl file. If you specified that your port was for role (not signal name) byteenable_n then 2'b00 is both bits asserted. If your add_port command specifies an active high byte enable then I would expect 2'b11. Again, measuring on the master will help debug here.

[Altera_Forum]

Thank you so much. My signal tap file was triggered by wrong signals. I do have same address mappinf for both reads and writes.