Simple circuit wont compile - why?

[Altera_Forum]

I am using Quartus 2 Web edition and have a cyclone II board. 

I am trying to run the first tutorial exercise and get errors with no reports.   LIBRARY ieee ; USE ieee.std_logic_1164.all; ENTITY Light IS PORT (x1, x2: IN STD_LOGIC; f : OUT STD_LOGIC); END Light; ARCHITECTURE LogicFunction OF Light IS BEGIN f<= (x1 AND NOT x2) OR (NOT x1 AND x2); End LogicFunction;   Error: Welcome to the Quartus II software. Thank you for choosing the# 1 software in performance and productivity. Error: Quartus II Full Compilation was unsuccessful. 1 error, 0 warnings   Any Ideas???

[Altera_Forum]

There's no problem with the code. It's either with your project or your Quartus configuration.

[Altera_Forum]

Please check file name of your VHDL source code. 

 VHDL source code file name = VHDL entity name  For example, light.vhd must have entity = light too

[Altera_Forum]

i've never seen that error. can you attach a .qar or .zip of the design?

[Altera_Forum]

--- Quote Start ---  Please check file name of your VHDL source code.  VHDL source code file name = VHDL entity name  For example, light.vhd must have entity = light too  --- Quote End ---    That is not a requirement and should not cause an error.

[Altera_Forum]

--- Quote Start ---  That is not a requirement and should not cause an error.  --- Quote End ---    Yes. Strictly spoken, the requirement is to set the top entity name in the Quartus project. If the top design file and top entity have the same name, you can simply click "Set as Top Entity" for the design file.