nios II processor interface with memory

[Altera_Forum]

Hi, 

 How do we connect three different memories to niosII processor so that we can access these three memories independently.

[Altera_Forum]

You can add each memory as a component in SOPC builder and connect them to the nios core. What do you mean by independently?

[Altera_Forum]

Hi, 

 Thanks for your suggestion.Independently means I want to access contents of first memory through nios II processor then second memory and so on... I want to interface RAM PORT 1 from megawizard plug in manager with niosII processor.Can you pls help me..  How to add memory as component in sopc builder? I read the SOPC user manual but not getting it. Pls help me...  thank you....

[Altera_Forum]

why don't you use the onchip memory from the SOPC builder components instead? It is the same than the RAM from the megawizard but with everything to connect it inside SOPC builder.

[Altera_Forum]

Hi, 

 Finally I am interested to use on-chip memory instead of RAM IP core from megawizard plug in manager. Please can you tell me how to write vhdl code for NiosII processor should write some ten data to on-chip memory? can I connect more than one on-chip memory to Nios II processor? I kindly request you to help me for the vhdl code.Please.....

[Altera_Forum]

You must use C code with the nios cpu, not vhdl. 

When you generate the bsp you will have a system.h file with some defines. One of them will be the name of your memory, with _BASE appended to it. This is the base address of the memory area, and you can use it to set the address of a C pointer. Then just use the pointer to read/write values in the memory. You can connect as many memories as you want to the CPU, as long as you have enough room in the FPGA for all of them.

[Altera_Forum]

hi, 

Thank you very much.Instead of C I want to use VHDL for writting and reading from on-chip RAM.Please can you tell me how to write vhdl code for this?I have created NIOS II processor with on chip ram.But I am not getting how to write vhdl code to read write the contents of on-chip RAM in quartus II project file.Please help me.

[Altera_Forum]

Do you want to share the memory between the Nios CPU and a hardware core you design? 

In that case you should design a custom SOPC component in VHDL using an Avalon Memory Mapped Master interface to access the ram. The RAM would be automatically shared between your component and the CPU, and your component would be independent from the type of memory it would access.

[Altera_Forum]

thread bump: hope this is okay ? 

 The "my_custom_vhdl_Base_adr" found in system.h on the nios side, provides an adr for "my_custom_vhdl" block so i can IOWR/IORD, to it from nios, but if i want to write(to some place in the onchip ram) from "my_custom_vhdl" and read(from some place in the on chip ram) from nios, how do you map that i Qsys and what VHDL would you use ?  /thanks in advance