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Incorrect data captured in SignalTap

Altera_Forum
Honored Contributor II
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Hi All, 

 

Strange problem here. I'm trying to debug a problem with my design using signal tap. 

The analyser only seems to sample accurate data for my attached nodes when I have the Nios debugger attached with a breakpoint set somewhere the main loop. Single stepping through my Nios code I can reliably capture accurate signal data. 

 

However, the problem I am trying to debug is rate dependent and requires the device to be fully running without breakpoints to show up the fault. But when I 'let it rip' (the NIOS code that is) whilst trying to capture signals in the signal tap, I get portions of the captured data correct, but most of it is complete garbage. Its almost like a buffer overflows or something as all data is correct up until a particular clock cycle, after which all the attached signals report random data. 

 

I have the correct clock domain assigned in signal tap, I'm using time quest and there are no timing violations on 'altera_internal_tck' reported. 

 

Its worth mentioning that I also get frequent dropouts in Nios IDE when debugging, which I suspect may be related to this. I don't however, EVER get ANY issues with programming or verification of the device over JTAG and I'm fairly sure that the JTAG circuit itself is sound since it has been used on other boards without any such issues. 

 

I'm using Cyclone III, QII v 10.0, Win 7. 

 

Can anyone suggest anything more to try???? 

 

Thanks
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