Using the global clock network in MAXII device

Altera_Forum · ‎06-08-2011

I have a clock signal that I need distributed to my components in a design. This is my first time using a MAXII, so I'm not very sure of myself here - I've made a simple clock signal that takes the on-board developer and divides by two, but I'm aware that clock delay may become a problem if I don't distribute the signal appropriately.

My clock divider code (currently)

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity CLOCK_DIVIDER is
    port(
        reset   :   in std_logic;
        clk :   in std_logic;
        half_clk    :   out std_logic
        );
end CLOCK_DIVIDER;
architecture CLOCK_DIVIDER of CLOCK_DIVIDER is
signal tick : std_logic;
begin
    process(clk, reset)
    begin
        if reset = '1' then
            tick <= '0';
        elsif clk = '1' and clk'EVENT then
            if tick = '0' then
                tick <= '1';
            elsif tick = '1' then
                tick <= '0';
            end if;
        end if;
    end process;
    process(tick)
    begin
        half_clk <= tick;
    end process
end CLOCK_DIVIDER;

clk comes from a pin with a signal from an external oscillator (PIN_H5). half_clk is routed to all my components but I'm not sure if it's using one of the four global clock networks that my data sheet tells me I have available - how do I make sure it uses a global net?

Altera_Forum · ‎06-08-2011

sorry but i don't have a answer of your problem but i have a question. how you interface your MaxII with the memory which is store the configuration of FPGA ??

thanks for your help.

Altera_Forum · ‎06-08-2011

I use a USB Blaster cable.

Altera_Forum · ‎06-08-2011

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but I'm aware that clock delay may become a problem if I don't distribute the signal appropriately.

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You can expect, that Quartus will assign global clock resources automatically, if appropriate. You usually don't care for this low level details. The delay between clk and half_clk will exist anyway, and possibly cause problems for signals crossing between both clock domains. Quartus timing analyzer will you inform about it, however.

The regular suggestion is to avoid clock dividers for internal clock signals and use divided clock enable signals instead.

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how you interface your MaxII with the memory which is store the configuration of FPGA

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Other than most FPGA, MAXII has internal non-volatile configuration memory.