Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Quartus Issue

Altera_Forum
Honored Contributor II
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Hi, 

 

I am working on a design which is implemented in Quartus 6.0 Version and it is working well. When I an upgrading this design to Quartus 7.1 Version it's not working.Actually there is H/W and S/W both so what i did in SOPC I added timer (high_res_temer(20 us) and sys_clk_timer(20 ms)) because without timer software was not going to build. These timers were not in Quartus 6.0 project. So can you please tell me what care i shoud take for upgradation in 7.1 version. 

Thanks in advance.
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