Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Strange error in Quartus 11.0

Altera_Forum
Honored Contributor II
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Hi,  

 

I'm using Quartus 11.0 for synthesis.  

 

I get a strange error when in my project I replace the entity/arch file of one of my sub-blocks for another (with exact same input signals and name) that has very minor differences (registered output instead of latch). 

 

The synthesis proceeeds normally but turns out incomplete when finished (with 0 errors !).  

 

Instead of producing ~5000 logic elements it produces 1000. When I look at the "Resource utilization by entity" tab, I see that some sub-blocks (other than the one whose file I replaced) do not appear and have not been synthesized by the tool.  

 

Any ideas ?  

 

D.
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Altera_Forum
Honored Contributor II
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You may have forgotten to connect a clock to some registers. 

You can check the message-window: it will warn you about such 'optimisations'
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