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Need help with parity checker!

Altera_Forum
Honored Contributor II
‎06-06-2011 08:09 AM
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Hi guys i'm totally new to VHDL and this is the start of my 2nd week learning it and i'm supposed to design a test and test bench on 8-bit parity checker (D0 to D7 as inputs) with 2 outputs (ouput_even and output_odd). When the sum of '1/HIGH's through D1-D7 is even, the output_even would show a HIGH while the output_odd would give a LOW. Likewise, when the sum of 1/HIGH's through D1-D7 is odd, output_even would show a LOW while output_odd would give a HIGH. Any takers? Please help! :confused:

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Altera_Forum
Honored Contributor II
‎06-06-2011 10:32 AM
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odd <= ((D0 xor D1) xor (D2 xor D3)) xor ((D4 xor D5) xor (D6 xor D7)); 

even <= not odd;
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Altera_Forum
Honored Contributor II
‎06-06-2011 12:27 PM
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Ok i totally get it now thanks so much!!! :D

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