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Stratix 3: SERDES PLL Questions

Altera_Forum
Honored Contributor II
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Hi All 

 

I have a design with multiple SERDES Tx and Rx links which requires to many Fast PLLs to fit in the designated Stratix 3 FPGA. There are some possible workarounds involving more unusual methods of sharing SERDES PLLs, but I don't know viable they are. Here are my questions: 

 

1) Can one PLL drive 3 SERDES Transmitters in an EP3SE110? What are the potential pitfalls? 

 

2) Is there any limit to the number of separate SERDES Transmitters and Receivers which can be placed on one side of an EP3SE110, other than the obvious limitation by number of LVDS pins? 

 

3) I have a 9-channel SERDES Receiver with a serialization of 4. Clock rate is 266MHz, serial data rate is thus 1064.  

(a) Can I use an internal 266 MHz clock for the SERDES Receiver PLL, rather than the external clock received with the serial data? 

(b) Note that this would mean clock to data skew of up to half a clock period (188 ps), or 2 bit times. Can DPA manage that in addition to the data-to-data skew introduced by a SERDES Transmitter in another FPGA, plus traces between 2 FPGAs on the same PCB? 

(c) Where do I get figures for max data to data skew, at the FPGA pins, for a SERDES Transmitter? 

 

4) Can I switch the clock input of a SERDES PLL, which is shared by both Receiver and Transmitter, between the clock received with the serial data, and an internal clock of the same frequency? 

 

Thanks, 

Chris
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