Architecture timing issue

[Altera_Forum]

Hi, 

In my architecture I need to do the following divider:   100000000/ (conv_integer (Byte_1 & Byte_2& Byte_3)) when stat_cycle='0'. (24 bits)   I'm working with 10Mhz clock. How do I know if the calculation will be quick enough for me to use the date immediately inside the process? (stat_cycle='0' at the end of the process and stat_cycle='1' will be in the next clock cycle)  Idan

[Altera_Forum]

Basically no. Dividers need several pipeline stages, which cannot be done with a simple "/" operator. You have to use a divider IP block.  

 Why do you need such a large divide (24 bits)?

[Altera_Forum]

iozana, 

It's hard to know beforehand exactly how much combinational and routing delay there is. You need to set a 10 MHz clock constrain , then synthesize the design (or the VHDL module) and run the static timing analysis (TimeQuest) to see if the constrains can be met.  Check the TimeQuest cookbook for details.  But experience tells us that in this particular case, no. A 24 bit divider is too big and has too much delay to run at 10 MHz in a single cycle. Thus, you need to pipeline the design or make it multi-cycle.  However, I'm not sure you need to use an IP block. If you pass the division's output through several levels of registers, Quartus is smart enough to distribute the combinatory logic through the several register levels.

[Altera_Forum]

Quartus cannot do register retiming for infered dividers, Ive tried, and raised an enhancement request. 

 Its only possible with infered multipliers.

[Altera_Forum]

i'm fairly certain one level of register retiming will work with a divider. multiple stages won't work (with anything)