Encrypted VHDL source

[Altera_Forum]

I have received an IP from supplier that is encrypted VHDL. 

Looks like this in the beginning: %%% protect protected_file %%% protect begin_protected %%% protect encoding=(enctype=base64)  The supplier states that Quartus is not able to use these files and that I am forced to go for Synopsys Synplify instead. I would rather like to not have to invest in another tool now but can Quartus manage this?  The files contain (I think) keys from Synplicity and Aldec. I guess it is the public key of a pair and the private is part of the tool?  I suppose in order to be able to use the files I would need them to encrypt the files for Quartus?   Has anybody any experience with this?

[Altera_Forum]

as far as i know Quartus II does not yet support VHDL-2008 encryption. you might file a Service Request to let Altera know that this feature is important to you, but i think you'll end up having to use Symplify for now

[Altera_Forum]

Hi similalrly does Quartus II support encrypted verilog source code? 

IEEE 1364-2005

[Altera_Forum]

this solution is kind of old, but it indicates no: 

 http://www.altera.com/support/kdb/solutions/rd10172006_472.html