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Hi guys, I've just started learning VHDL for a week on my own so i'm still very new to it. I'm doing a practice on implementing a 4-bit parallel-out serial shift register.. My codings can be complied but it shows
" # ** Fatal: (vsim-3347) Port 'din' is not constrained.# Time: 0 ns Iteration: 0 Instance: /shiftreg File: /EDCP6/proj15/jianhua/vhdl/Lab3_compare.vhd Line: 5# FATAL ERROR while loading design " when i tried to simulate it. can anyone help me out with this? ************************************************** ********************************************* library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity shiftreg is port ( din: in std_logic_vector; -- data in clk: in std_logic; -- Clock clr: in std_logic; -- Clear pset: in std_logic; --Preset q : out std_logic_vector(3 downto 0) -- output Q ); end; architecture rtl of shiftreg is begin process (clk, clr,pset) begin if (pset='0') then q <= "1111"; elsif (clr='0') then q <= "0000"; elsif (clk'event and clk = '1') then q <= din; end if; end process; end rtl;Link Copied
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Trydin: in std_logic_vector(3 downto 0); -- data in
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Hi daixiwen (http://www.alteraforum.com/forum/member.php?u=4443)! Thanks for replying my thread.
I realised i had left out the input length but for my case, i have a 2-bit input (AND gate) and it does not match with the 4-bit output! Instead i tried forcing my inputs to a LOW but then again i realised, i need to be able to switch my input to a HIGH too. Any idea on what should i do?
din1: in std_logic_vector:="0" ;
din2: in std_logic_vector:="0" ;
This was what i did but i couldn't force it a high when after simulating it! What should i do? :confused:
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why have you declared a std_logic_vector of only 1 bit? you really should give it a fixed length, otherwise its really just a std_logic
If you need to change the value during simulation, you should write a testbench. Your post here is not very clear. If you have a 4 bit output, you need to connect all 4 bits to something.- Mark as New
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Thanks for the help Tricky! I got it working now.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shiftreg is port (
A: in std_logic; -- data in
B: in std_logic;
clk: in std_logic; -- Clock
clr: in std_logic; -- Clear
preset: in std_logic; --Preset
q : out std_logic_vector(3 downto 0) -- output Q
);
end;
architecture rtl of shiftreg is
signal q_int : std_logic_vector(3 downto 0);
begin
process (clk, clr,preset)
begin
if (preset='0') then
q_int <= "1111";
elsif (clr='0') then
q_int <= "0000";
elsif (clk'event and clk = '1') then
q_int(0) <= A and B;
q_int(1) <= q_int(0);
q_int(2) <= q_int(1);
q_int(3) <= q_int(2);
end if;
end process;
q <= q_int;
end rtl;
Bu how do i write a test bench? I tried writing one myself i think it's pretty messed up and it doesn't seem to produce the waveform i wanted. Testbench Library IEEE;
Use IEEE.std_logic_1164.all;
Entity shiftregTB is
end;
Architecture rtl of shiftregTB is
signal A,B,clk,clr,preset: std_logic;
signal q,q_int : std_logic_vector(3 downto 0);
begin
UUT : entity work.shiftreg port map(A,B,clk,clr,preset,q_int);
tb : process
begin
preset<='0';
wait for 10 ns;
preset<='1';
wait for 10 ns;
clr<='0';
wait for 20 ns;
clr<='1';
wait for 20 ns;
clk<='1';
wait for 20 ns;
A<='1';
wait for 30 ns;
B<='1';
wait for 30 ns;
A<='0';
wait for 40 ns;
B<= '0';
wait for 50 ns;
end process tb;
q<=q_int;
end;
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your test bench is a good starting point. It is usually easier to generate the clock in a separate process and concentrate on the other signals in your main test bench process.
What are the differences between what you want and what you get?
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