I/Os timing constraints between FPGA and SDR SDRAM

[Altera_Forum]

Hello, i'm sorry my english is not so good. 

 I'm working on a sdr sdram controller. The board is a demo stratix development kit. The fpga is the EP1S10F780C6 and the sdram is the MT48LC4M32B2. The main clock runs at 50Mhz.   I would like to know how can I constraint data in common between the fpga and the sdram i.e : data_in_out, DQM, clk_sdram, CKE, BA, Address, CS, CAS, RAS and WE.  What I want to do is to use the atpll IP on quartus, to synchronize data from fpga and SDRAM clock. I use the zero delay buffer option of the pll and fast input/output registers.  To estimate the location and duration of the valid signal window i need to know the timing parameters provided in the Quartus II software compilation report. My problem is that i'm not able to interpret them correctly.  So i'm looking in the Datasheet report of the TimeQuest Timing analyzer menu. I find :  Setup Times:  Data_in_out[*] : 1.528  Hold times : Data_in_out[*] : -1.373  Clock to output times: Address[*] : 9.505 DQM[*] : 6.050 Data_in_out[*] : 6.084 CAS : 6.055 CS : 6.061 RAS : 6.050 We : 6.061  Minimum clock to output times :  Address[*] : 8.105 CAS : 6.061 CS : 6.061 DQM[*] : 6.050 Data_in_out[*] : 6.050 RAS : 6.050 WE : 6.061  I saw on altera.co.jp/literature/hb/nios2/n2cpu_nii51005.pdf that i need : the clock period,  the minimum clock-to-output time, the maximum clock-to-output time, the maximum hold time after clock, and the maximum setup time before clock.  But regarding the setup time I thought that 1.528 ns was the minimum tsu so how can i find the maximum value? Then i guess minimum tco is 8.105, the max tco is 9.505 and th min -1.373. Am I right?  On my .sdc file I wrote :  create_clock -name "Main_clk" -period 20.000ns [get_ports {H}] create_clock -name "virt_clk" -period 20.000ns set_input_delay -clock "Main_clk" -max 1.528ns [get_ports {H}] set_input_delay -clock "Main_clk" -min 0ns [get_ports {H}]  derive_pll_clocks -create_base_clocks  set_input_delay -clock "virt_clk" -max 1.748ns [get_ports {Data_in_out[*] init start}]  set_input_delay -clock "virt_clk" -min -0ns [get_ports {Data_in_out[*] init start}]   set_output_delay -clock "virt_clk" -max 4.55ns [get_ports {Address[*] CS CKE CAS BA[*] Data_in_out[*] DQM[*] RAS We}]  set_output_delay -clock "virt_clk" -min 2.0ns [get_ports {Address[*] CS CKE CAS BA[*] Data_in_out[*] DQM[*] RAS We}]    I don't know how to set the constraints according to the datasheet report. For example for the set_out_delay -max, if the value is upper than 4.55 ns i don't meet the timings. Then I used virtual clock but I don't know if it's correct, i saw that's it's important to do this way. And i didn't make any constraint for the clk out, is it correct ? How can I do it?  My last question is about the SDRAM device. Timings depend on CL and speed grade. I'm using it with CL=3 and I'm not sure about the speed grade. How can I find it? It's 6 or 7.  Thank you for your consideration.