Verilog Compilation Problem: All available logic elements used!

[Altera_Forum]

Hi all, 

 I am having a problem compiling my verilog code in Quartus II where all the available logic elements (12'060) are used by the compiler.  The code (excerpt) is as follows:  begin  if (Address[0] == 1 && Address[1] == 0)     begin     //TimerFlag <= 1'd1;     contCount <= 16'd0;     end else  begin     if (TimerFlag == 1)         begin      if (Address[1] == 1)          begin             TimerFlag <= 1'd0;             //Timings[PtrT] = contCount;             //PtrT = PtrT + 8'd1;             end  //else contCount <= contCount + 16'd1;  end[/INDENT]  else ;  end[/INDENT] end   note: If any one of the hashed ( // ) lines are removed, the code compiles normally (only ~1500 of the logic elements are used).

[Altera_Forum]

The shown code excerpt is effectively meaningless, because the design functions causing the large resource utilization are obviously outside this text. 

 By commenting the said lines, you force some signals to constant values, which in turn disables the code depending on these signals. A synthesis compiler is very clever in omitting any unused logic.

[Altera_Forum]

Sorry, I guess I forgot to add into my post: 

  reg [15:0] Timings [255:0];  reg [ 7:0] PtrT;  reg TimerFlag;  reg [15:0] contCount;   I think it is the large array that is causing my problem, however I need my device to store a large array and also not use all the logic elements :D is there some code that I need to know in order to store the array in the 239'616 "memory bits" rather than in logic elements?  Dan

[Altera_Forum]

--- Quote Start ---  I think it is the large array that is causing my problem  --- Quote End ---   That sounds plausible, because the implementation will need a large amount of combinational logic to mux and demux data to each of the 4096 memory bits.  Using internal RAM is the obvious solution, involving a much smaller logic utilization footprint. You have to keep the requirements for RAM inference however. The most serious restriction is, that at maximum two (in case of a dual port RAM) memory addresses can be accessed at a time, also the synchronous character of memory access must be observed.   To get an idea how it works, you can use the VHDL or Verilog RAM usage templates available in the Quartus IDE.